Here is the instruction and hex set and outlay of the whole intel 8051 series... which includes our friend mr. robot-eeprom ;p enjoy!! INTEL HEX FORMAT DATA RECORD --- BYTE # 1 Colon (:), signifies start of a record. 2 & 3 Number of data bytes in this record. 4 & 5 Load address for this record, High Byte. 6 & 7 Load address for this record, Low Byte. 8 & 9 Record type, must be "00". 10 to X Data bytes, two ASCII hex characters each. X+1 & X+2 Checksum, two ASCII hex characters. X+3 & X+4 CR & LF, (carriage return & line-feed). END RECORD --- BYTE # 1 Colon (:), signifies start of a record. 2 & 3 Record length, must be "00". 4 to 7 Start address, "0000" = end record. 8 & 9 Record type 10 & 11 Checksum, two ASCII hex characters. 12 & 13 CR & LF, (carriage return & line-feed). The CHECKSUM is the two's complement of the 8-bit sum of the Record Length, the two byte Load Address, the Record Type, and all the Data bytes. 3.1 8051 INSTRUCTION SET - ARITHMETIC OPERATIONS Assembly form Byte/Cycle Flags,Notes Description _________________________________________________________________________ ADD A,Rn 1/1 AC,CY,OV Add Register to Accumulator ADD A,direct 2/1 AC,CY,OV Add Direct Byte to Accumulator ADD A,@Ri 1/1 AC,CY,OV Add Indirect RAM to Accumulator ADD A,#data 2/1 AC,CY,OV Add Immediate Data to Accumulator ADDC A,Rn 1/1 AC,CY,OV Add Register to Acc with Carry ADDC A,direct 2/1 AC,CY,OV Add Direct Byte to Acc with Carry ADDC A,@Ri 1/1 AC,CY,OV Add Indirect RAM to Acc with Carry ADDC A,#data 2/1 AC,CY,OV Add Immediate Data to Acc with Carry DA A 1/1 CY,4 Decimal Adjust Accumulator DEC A 1/1 Decrement Accumulator DEC Rn 1/1 Decrement Register DEC direct 2/1 Decrement Direct Byte DEC @Ri 1/1 Decrement Indirect RAM DIV AB 1/4 CY=0,OV,5 Divide Accumulator by B Register INC A 1/1 Increment Accumulator INC Rn 1/1 Increment Register INC direct 2/1 Increment Direct Byte INC @Ri 1/1 Increment Indirect RAM INC DPTR 1/2 Increment Data Pointer MUL AB 1/4 CY=0,OV,7 Multiply Accumulator and B Register SUBB A,Rn 1/1 AC,CY,OV Subtract Register from Acc w/borrow SUBB A,direct 2/1 AC,CY,OV Sub Direct Byte from Acc w/borrow SUBB A,@Ri 1/1 AC,CY,OV Sub Indirect RAM from Acc w/borrow SUBB A,#data 2/1 AC,CY,OV Sub Immediate Data from Acc w/borrow 3.2 8051 INSTRUCTION SET - LOGICAL OPERATIONS Assembly form Byte/Cycle Flags,Notes Description _________________________________________________________________________ ANL A,Rn 1/1 AND Register to Accumulator ANL A,direct 2/1 AND Direct Byte to Accumulator ANL A,@Ri 1/1 AND Indirect RAM to Accumulator ANL A,#data 2/1 AND Immediate Data to Accumulator ANL direct,A 2/1 AND Accumulator to Direct Byte ANL direct,#data 3/2 AND Immediate Data to Direct Byte CLR A 1/1 Clear Accumulator CPL A 1/1 Complement Accumulator ORL A,Rn 1/1 OR Register to Accumulator ORL A,direct 2/1 OR Direct Byte to Accumulator ORL A,@Ri 1/1 OR Indirect RAM to Accumulator ORL A,#data 2/1 OR Immediate Data to Accumulator ORL direct,A 2/1 OR Accumulator to Direct Byte ORL direct,#data 3/2 OR Immediate Data to Direct Byte RL A 1/1 Rotate Accumulator Left RLC A 1/1 CY Rotate Acc Left through Carry RR A 1/1 Rotate Accumulator Right RRC A 1/1 CY Rotate Acc Right through Carry SWAP A 1/1 Swap Nibbles within the Accumulator XRL A,Rn 1/1 Exclusive-OR Register to Accumulator XRL A,direct 2/1 Exclusive-OR Direct Byte to Acc XRL A,@Ri 1/1 Exclusive-OR Indirect RAM to Acc XRL A,#data 2/1 Exclusive-OR Immediate Data to Acc XRL direct,A 2/1 Exclusive-OR Acc to Direct Byte XRL direct,#data 3/2 Exclusive-OR Imm Data to Direct Byte 3.3 8051 INSTRUCTION SET - DATA TRANSFER Assembly form Byte/Cycle Flags,Notes Description _________________________________________________________________________ MOV A,Rn 1/1 Move Register to Accumulator MOV A,direct 2/1 Move Direct Byte to Accumulator MOV A,@Ri 1/1 Move Indirect RAM to Accumulator MOV A,#data 2/1 Move Immediate Data to Accumulator MOV Rn,A 1/1 Move Accumulator to Register MOV Rn,direct 2/2 Move Direct Byte to Register MOV Rn,#data 2/1 Move Immediate Data to Register MOV direct,A 2/1 Move Accumulator to Direct Byte MOV direct,Rn 2/2 Move Register to Direct Byte MOV direct,direct 3/2 Move from Direct Byte to Direct Byte MOV direct,@Ri 2/2 Move Indirect RAM to Direct Byte MOV direct,#data 3/2 Move Immediate Data to Direct Byte MOV @Ri,A 1/1 Move Accumulator to Indirect RAM MOV @Ri,direct 2/2 Move Direct Byte to Indirect RAM MOV @Ri,#data 2/1 Move Immediate Data to Indirect RAM MOV DPTR,#data16 3/2 Load Data Pointer w/ 16-bit Constant MOVC A,@A+DPTR 1/2 Move Code Byte relative DPTR to Acc MOVC A,@A+PC 1/2 Move Code Byte relative to PC to Acc POP direct 2/2 Pop Direct Byte from Stack PUSH direct 2/2 Push Direct Byte onto Stack XCH A,Rn 1/1 Exchange Register with Accumulator XCH A,direct 2/1 Exchange Direct Byte with Accumulator XCH A,@Ri 1/1 Exchange Indirect RAM with Acc XCHD A,@Ri 1/1 Exchange Low Nibble Ind RAM with Acc 3.4 8051 INSTRUCTION SET - BOOLEAN VARIABLE MANIPULATION Assembly form Byte/Cycle Flags,Notes Description _________________________________________________________________________ ANL C,bit 2/2 CY AND Direct Bit to Carry ANL C,/bit 2/2 CY AND complement of Direct Bit to Cy CLR C 1/1 CY Clear Carry CLR bit 2/1 Clear Direct Bit CPL C 1/1 CY Complement Carry CPL bit 2/1 Complement Direct Bit JB bit,rel 3/2 Jump if Direct Bit is set JNB bit,rel 3/2 Jump if Direct Bit is Not set JBC bit,rel 3/2 AC,CY,OV,6 Jump if Direct Bit set then Clear it JC rel 2/2 Jump if Carry is set JNC rel 2/2 Jump if Carry is Not set MOV C,bit 2/1 CY Move Direct Bit to Carry MOV bit,C 2/2 Move Carry to Direct Bit ORL C,bit 2/2 CY OR Direct Bit to Carry ORL C,/bit 2/2 CY OR complement of Direct Bit to Carry SETB C 1/1 CY Set Carry SETB bit 2/1 Set Direct Bit 3.5 8051 INSTRUCTION SET - PROGRAM BRANCHING Assembly form Byte/Cycle Flags,Notes Description _________________________________________________________________________ ACALL addr 11 2/2 1 Absolute Subroutine Call, 11-bit addr AJMP addr 11 2/2 2 Absolute Jump, 11-bit address CJNE A,direct,rel 3/2 CY,3 Comp Dir Byte to Acc, Jmp not equal CJNE A,#data,rel 3/2 CY,3 Compare Immed to Acc & Jump not equal CJNE Rn,#data,rel 3/2 CY,3 Compare Immed to Reg & Jump not equal CJNE @Ri,#data,rel3/2 CY,3 Comp Imm to Indir Ri, Jump not equal DJNZ Rn,rel 2/2 Decrement Register & Jump if not zero DJNZ direct,rel 3/2 Decrement Direct Byte & Jump not zero JMP @A+DPTR 1/2 Jump indirect relative to the DPTR JNZ rel 2/2 Jump if Accumulator is Not Zero JZ rel 2/2 Jump if Accumulator is Zero LCALL addr 16 3/2 Long Subroutine Call, 16-bit Address LJMP addr 16 3/2 Long Jump, 16-bit Address NOP 1/1 No Operation RET 1/2 Return from subroutine RETI 1/2 Return from Interrupt SJMP rel 2/2 Short Jump, relative address NOTES 1. Starting with 11H as the opcode base, the final opcode is formed by placing bits 8, 9, and 10 of the target address in bits 5, 6, and 7 of the opcode. The 8 possible opcodes in hexadecimal are then: 11, 31, 51, 71, 91, B1, D1, F1 2. Starting with 01H as the opcode base, the final opcode is formed by placing bits 8, 9, and 10 of the target address in bits 5, 6, and 7 of the opcode. The 8 possible opcodes in hexadecimal are then: 01, 21, 41, 61, 81, A1, C1, E1 3. The Carry Flag is set if the Destination Operand is less than the Source Operand, otherwise the Carry Flag is clear. 4. The Carry Flag is set if the BCD result in the Accumulator is greater than decimal 99. 5. The Overflow Flag is set if the B Register contains zero (flags a divide by zero operation). Otherwise the Overflow Flag is cleared. 6. If any of the condition code flags are specified as the operand of this instruction, they will be reset by the instruction if they were originally set. 7. The high byte of the 16-bit product is placed in the B Register, the low byte in the Accumulator. NOTES ON THE INSTRUCTION SET AND THE ADDRESSING MODES addr 11 - 11-bit destination address. Used by ACALL and AJMP. Branch will be within the same 2K-byte page of Program Memory as the first byte of the following instruction. addr 16 - 16-bit destination address. Used by LCALL and LJMP. A branch can be anywhere within the 64K-byte Program Memory address space. bit - Direct Addressed bit in Internal Data RAM or Special Function Register. direct - 8-bit internal data location's address. This could be an Internal Data RAM location (0-127) or an SFR [i.e., I/O port, control register, status register, ect.(128-255)]. rel - Signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps. Range is -128 to +127 bytes relative to first byte of the following instruction. Rn - Register R0-R7 of the currently selected Register Bank. @Ri - 8-bit internal data RAM location (0-255) addressed indirectly through register R0 or R1. #data - 8-bit constant included in instruction. #data 16 - 16-bit constant included in instruction. 3.6 SPECIAL FUNCTION REGISTER MAP M: 80= P0 M: A0= P2 M: C0= M: E0= ACC M: 81= SP M: A1= M: C1= M: E1= M: 82= DPL M: A2= M: C2= M: E2= M: 83= DPH M: A3= M: C3= M: E3= M: 84= M: A4= M: C4= M: E4= M: 85= M: A5= M: C5= M: E5= M: 86= M: A6= M: C6= M: E6= M: 87= PCON M: A7= M: C7= M: E7= M: 88= TCON M: A8= IE M: C8= T2CON M: E8= M: 89= TMOD M: A9= M: C9= M: E9= M: 8A= TL0 M: AA= M: CA= RCAP2L M: EA= M: 8B= TL1 M: AB= M: CB= RCAP2H M: EB= M: 8C= TH0 M: AC= M: CC= TL2 M: EC= M: 8D= TH1 M: AD= M: CD= TH2 M: ED= M: 8E= M: AE= M: CE= M: EE= M: 8F= M: AF= M: CF= M: EF= M: 90= P1 M: B0= P3 M: D0= PSW M: F0= B M: 91= M: B1= M: D1= M: F1= M: 92= M: B2= M: D2= M: F2= M: 93= M: B3= M: D3= M: F3= M: 94= M: B4= M: D4= M: F4= M: 95= M: B5= M: D5= M: F5= M: 96= M: B6= M: D6= M: F6= M: 97= M: B7= M: D7= M: F7= M: 98= SCON M: B8= IP M: D8= M: F8= M: 99= SBUF M: B9= M: D9= M: F9= M: 9A= M: BA= M: DA= M: FA= M: 9B= M: BB= M: DB= M: FB= M: 9C= M: BC= M: DC= M: FC= M: 9D= M: BD= M: DD= M: FD= M: 9E= M: BE= M: DE= M: FE= M: 9F= M: BF= M: DF= M: FF= 3.7 BIT ADDRESSABLE REGISTER MAP B: 80= P0.0 B: A0= P2.0 B: C0= B: E0= ACC.0 B: 81= P0.1 B: A1= P2.1 B: C1= B: E1= ACC.1 B: 82= P0.2 B: A2= P2.2 B: C2= B: E2= ACC.2 B: 83= P0.3 B: A3= P2.3 B: C3= B: E3= ACC.3 B: 84= P0.4 B: A4= P2.4 B: C4= B: E4= ACC.4 B: 85= P0.5 B: A5= P2.5 B: C5= B: E5= ACC.5 B: 86= P0.6 B: A6= P2.6 B: C6= B: E6= ACC.6 B: 87= P0.7 B: A7= P2.7 B: C7= B: E7= ACC.7 B: 88= IT0 B: A8= EX0 B: C8= T2CP B: E8= B: 89= IE0 B: A9= ET0 B: C9= T2C B: E9= B: 8A= IT1 B: AA= EX1 B: CA= TR2 B: EA= B: 8B= IE1 B: AB= ET1 B: CB= EXEN2 B: EB= B: 8C= TR0 B: AC= ES B: CC= TCLK B: EC= B: 8D= TF0 B: AD= ET2 B: CD= RCLK B: ED= B: 8E= TR1 B: AE= B: CE= EXF2 B: EE= B: 8F= TF1 B: AF= EA B: CF= TF2 B: EF= B: 90= P1.0 B: B0= P3.0 B: D0= P B: F0= B.0 B: 91= P1.1 B: B1= P3.1 B: D1= B: F1= B.1 B: 92= P1.2 B: B2= P3.2 B: D2= OV B: F2= B.2 B: 93= P1.3 B: B3= P3.3 B: D3= RS0 B: F3= B.3 B: 94= P1.4 B: B4= P3.4 B: D4= RS1 B: F4= B.4 B: 95= P1.5 B: B5= P3.5 B: D5= F0 B: F5= B.5 B: 96= P1.6 B: B6= P3.6 B: D6= AC B: F6= B.6 B: 97= P1.7 B: B7= P3.7 B: D7= CY B: F7= B.7 B: 98= RI B: B8= PX0 B: D8= B: F8= B: 99= TI B: B9= PT0 B: D9= B: F9= B: 9A= RB8 B: BA= PX1 B: DA= B: FA= B: 9B= TB8 B: BB= PT1 B: DB= B: FB= B: 9C= REN B: BC= PS B: DC= B: FC= B: 9D= SM2 B: BD= PT2 B: DD= B: FD= B: 9E= SM1 B: BE= B: DE= B: FE= B: 9F= SM0 B: BF= B: DF= B: FF= 3.8 SPECIAL FUNCTION REGISTER ASSIGNMENTS Reg Byte Bit Address Byte / Bit Name Addr 7 6 5 4 3 2 1 0 Description ------ ---- --------------------------------- -------------------------- P0 80 87 86 85 84 83 82 81 80 Port 0 | | | | | | | +--> P0.0 Port 0 bit 0 | | | | | | +------> P0.1 Port 0 bit 1 | | | | | +----------> P0.2 Port 0 bit 2 | | | | +--------------> P0.3 Port 0 bit 3 | | | +------------------> P0.4 Port 0 bit 4 | | +----------------------> P0.5 Port 0 bit 5 | +--------------------------> P0.6 Port 0 bit 6 +------------------------------> P0.7 Port 0 bit 7 SP 81 - - - - - - - - Stack Pointer DPL 82 - - - - - - - - Data Pointer Low (DPTR) DPH 83 - - - - - - - - Data Pointer High (DPTR) PCON 87 - - - - - - - - Power Control register | | | | | | | +--> IDL Idle mode bit | | | | | | +------> PD Power down bit | | | | | +----------> GF0 General Purpose flag | | | | +--------------> GF1 General Purpose flag | | | +------------------> | | +----------------------> | +--------------------------> +------------------------------> SMOD Double Baud Rate bit TCON 88 8F 8E 8D 8C 8B 8A 89 88 Timer / Counter control | | | | | | | +--> IT0 INT0 edge control | | | | | | +------> IE0 INT0 edge detect flag | | | | | +----------> IT1 INT1 edge control | | | | +--------------> IE1 INT1 edge detect flag | | | +------------------> TR0 Timer 0 run control | | +----------------------> TF0 Timer 0 overflow flag | +--------------------------> TR1 Timer 1 run control +------------------------------> TF1 Timer 1 overflow flag TMOD 89 - - - - - - - - Timer /Counter Mode Control | | | | | | | +--> M0 Timer 0 operate mode | | | | | | +------> M1 Timer 0 operate mode | | | | | +----------> C/T Counter/Timer 0 slct | | | | +--------------> GATE Timer 0 gate | | | +------------------> M0 Timer 1 operate mode | | +----------------------> M1 Timer 1 operate mode | +--------------------------> C/T Counter/Timer 1 slct +------------------------------> GATE Timer 1 gate SPECIAL FUNCTION REGISTER ASSIGNMENTS (cont.) Reg Byte Bit Address Byte / Bit Name Addr 7 6 5 4 3 2 1 0 Description ------ ---- --------------------------------- -------------------------- TL0 8A - - - - - - - - Timer / Counter 0 low byte TL1 8B - - - - - - - - Timer / Counter 1 low byte TH0 8C - - - - - - - - Timer / Counter 0 high byte TH1 8D - - - - - - - - Timer / Counter 1 high byte P1 90 97 96 95 94 93 92 91 90 Port 1 | | | | | | | +--> P1.0 Port 1 bit 0 | | | | | | +------> P1.1 Port 1 bit 1 | | | | | +----------> P1.2 Port 1 bit 2 | | | | +--------------> P1.3 Port 1 bit 3 | | | +------------------> P1.4 Port 1 bit 4 | | +----------------------> P1.5 Port 1 bit 5 | +--------------------------> P1.6 Port 1 bit 6 +------------------------------> P1.7 Port 1 bit 7 SCON 98 9F 9E 9D 9C 9B 9A 99 98 Serial Control | | | | | | | +--> RI Rcvr interrupt flag | | | | | | +------> TI Xmit interrupt flag | | | | | +----------> RB8 9th bit rcvd/stop bit | | | | +--------------> TB8 9th bit transmission | | | +------------------> REN Receiver enable | | +----------------------> SM2 Serial Port mode slct | +--------------------------> SM1 Serial Port mode slct +------------------------------> SM0 Serial Port mode slct SBUF 99 - - - - - - - - Serial Data Buffer P2 A0 A7 A6 A5 A4 A3 A2 A1 A0 Port 2 | | | | | | | +--> P2.0 Port 2 bit 0 | | | | | | +------> P2.1 Port 2 bit 1 | | | | | +----------> P2.2 Port 2 bit 2 | | | | +--------------> P2.3 Port 2 bit 3 | | | +------------------> P2.4 Port 2 bit 4 | | +----------------------> P2.5 Port 2 bit 5 | +--------------------------> P2.6 Port 2 bit 6 +------------------------------> P2.7 Port 2 bit 7 SPECIAL FUNCTION REGISTER ASSIGNMENTS (cont.) Reg Byte Bit Address Byte / Bit Name Addr 7 6 5 4 3 2 1 0 Description ------ ---- --------------------------------- -------------------------- IE A8 AF AE AD AC AB AA A9 A8 Interrupt Enable register | | | | | | | +--> EX0 Enable interrupt INT0 | | | | | | +------> ET0 Timer 0 overflow int. | | | | | +----------> EX1 Enable interrupt INT1 | | | | +--------------> ET1 Timer 1 overflow int. | | | +------------------> ES Serial Port interrupt | | +----------------------> ET2 Timer 2 ovflow or Cap | +--------------------------> +------------------------------> EA Enable all interrupts P3 B0 B7 B6 B5 B4 B3 B2 B1 B0 Port 3 | | | | | | | +--> P3.0 Port 3 bit 0 | | | | | | +------> P3.1 Port 3 bit 1 | | | | | +----------> P3.2 Port 3 bit 2 | | | | +--------------> P3.3 Port 3 bit 3 | | | +------------------> P3.4 Port 3 bit 4 | | +----------------------> P3.5 Port 3 bit 5 | +--------------------------> P3.6 Port 3 bit 6 +------------------------------> P3.7 Port 3 bit 7 IP B8 BF BE BD BC BB BA B9 B8 Interrupt Priority Control | | | | | | | +--> PX0 INT0 priority | | | | | | +------> PT0 Timer 0 priority | | | | | +----------> PX1 INT1 priority | | | | +--------------> PT1 Timer 1 priority | | | +------------------> PS Serial Port priority | | +----------------------> PT2 Timer 2 priority | +--------------------------> +------------------------------> T2CON C8 CF CE CD CC CB CA C9 C8 Timer / Counter 2 control | | | | | | | +--> T2CP Capture/reload flag | | | | | | +------> T2C Internal/Ext select | | | | | +----------> TR2 Timer 2 start/stop | | | | +--------------> EXEN2 Timer 2 ext enable | | | +------------------> TCLK Transmit clock flag | | +----------------------> RCLK Receive clock flag | +--------------------------> EXF2 Timer 2 external flag +------------------------------> TF2 Timer 2 overflow flag SPECIAL FUNCTION REGISTER ASSIGNMENTS (cont.) Reg Byte Bit Address Byte / Bit Name Addr 7 6 5 4 3 2 1 0 Description ------ ---- --------------------------------- -------------------------- RCAP2L CA - - - - - - - - T/C 2 Capture reg. low byte RCAP2H CB - - - - - - - - T/C 2 Capt reg. high byte TL2 CC - - - - - - - - Timer / Counter 2 low byte TH2 CD - - - - - - - - Timer / Counter 2 high byte PSW D0 D7 D6 D5 D4 D3 D2 D1 D0 Program Status Word | | | | | | | +--> P ACC parity flag | | | | | | +------> -- User definable flag | | | | | +----------> OV Overflow flag | | | | +--------------> RS0 Reg bank select 0 | | | +------------------> RS1 Reg bank select 1 | | +----------------------> F0 Gen purpose Flag 0 | +--------------------------> AC Auxiliary carry flag +------------------------------> CY Carry flag ACC E0 E7 E6 E5 E4 E3 E2 E1 E0 Accumulator | | | | | | | +--> ACC.0 Accumulator bit 0 | | | | | | +------> ACC.1 Accumulator bit 1 | | | | | +----------> ACC.2 Accumulator bit 2 | | | | +--------------> ACC.3 Accumulator bit 3 | | | +------------------> ACC.4 Accumulator bit 4 | | +----------------------> ACC.5 Accumulator bit 5 | +--------------------------> ACC.6 Accumulator bit 6 +------------------------------> ACC.7 Accumulator bit 7 B F0 F7 F6 F5 F4 F3 F2 F1 F0 B Register | | | | | | | +--> B.0 B register bit 0 | | | | | | +------> B.1 B register bit 1 | | | | | +----------> B.2 B register bit 2 | | | | +--------------> B.3 B register bit 3 | | | +------------------> B.4 B register bit 4 | | +----------------------> B.5 B register bit 5 | +--------------------------> B.6 B register bit 6 +------------------------------> B.7 B register bit 7 3.10 INTERRUPT VECTORS & PRIORITY LEVELS Event Vector Priority level ------------------- ------ ----------------- Reset 000 External INT0 003 - Highest priority Counter / Timer 0 00B External INT1 013 Counter / Timer 1 01B Serial RCV & XMIT flag 023 Timer 2 & External 2 02B - Lowest priority 3.11 USER RAM MEMORY MAP Byte Bit Address Byte / Bit Addr 7 6 5 4 3 2 1 0 Description -------- --------------------------------- --------------------------- 30 -> 7F - - - - - - - - 80 bytes general user RAM 2F 7F 7E 7D 7C 7B 7A 79 78 Bit addressable RAM location 2E 77 76 75 74 73 72 71 70 Bit addressable RAM location 2D 6F 6E 6D 6C 6B 6A 69 68 Bit addressable RAM location 2C 67 66 65 64 63 62 61 60 Bit addressable RAM location 2B 5F 5E 5D 5C 5B 5A 59 58 Bit addressable RAM location 2A 57 56 55 54 53 52 51 50 Bit addressable RAM location 29 4F 4E 4D 4C 4B 4A 49 48 Bit addressable RAM location 28 47 46 45 44 43 42 41 40 Bit addressable RAM location 27 3F 3E 3D 3C 3B 3A 39 38 Bit addressable RAM location 26 37 36 35 34 33 32 31 30 Bit addressable RAM location 25 2F 2E 2D 2C 2B 2A 29 28 Bit addressable RAM location 24 27 26 25 24 23 22 21 20 Bit addressable RAM location 23 1F 1E 1D 1C 1B 1A 19 18 Bit addressable RAM location 22 17 16 15 14 13 12 11 10 Bit addressable RAM location 21 0F 0E 0D 0C 0B 0A 09 08 Bit addressable RAM location 20 07 06 05 04 03 02 01 00 Bit addressable RAM location 18 -> 1F - - - - - - - - Bank 3 registers R0 -> R7 10 -> 17 - - - - - - - - Bank 2 registers R0 -> R7 08 -> 0F - - - - - - - - Bank 1 registers R0 -> R7 00 -> 07 - - - - - - - - Bank 0 registers R0 -> R7