<dec f='src/src/sys/external/bsd/drm2/dist/drm/radeon/atombios.h' l='1705' type='ULONG'/>
<offset>96</offset>
<doc f='src/src/sys/external/bsd/drm2/dist/drm/radeon/atombios.h' l='1698'>// bit[1]= when VGA timing is used. 
                             // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
                             // bit[4]= RefClock source for PPLL. 
                             // =0: XTLAIN( default mode )
	                           // =1: other external clock source, which is pre-defined                                            
                             //     by VBIOS depend on the feature required.
                             // bit[7:5]: reserved.</doc>
<doc f='src/src/sys/external/bsd/drm2/dist/drm/radeon/atombios.h' l='1705'>// 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )</doc>
<use f='src/src/sys/external/bsd/drm2/dist/drm/radeon/atombios_crtc.c' l='883' u='w' c='atombios_crtc_program_pll'/>
