<dec f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.h' l='1322' type='atomic_t'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.h' l='2431' u='a' c='i915_reset_in_progress'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.h' l='2437' u='a' c='i915_terminally_wedged'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.h' l='2442' u='a' c='i915_reset_count'/>
<offset>1088</offset>
<doc f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.h' l='1301'>/**
	 * State variable controlling the reset flow and count
	 *
	 * This is a counter which gets incremented when reset is triggered,
	 * and again when reset has been handled. So odd values (lowest bit set)
	 * means that reset is in progress and even values that
	 * (reset_counter &gt;&gt; 1):th reset was successfully completed.
	 *
	 * If reset is not completed succesfully, the I915_WEDGE bit is
	 * set meaning that hardware is terminally sour and there is no
	 * recovery. All waiters on the reset_queue will be woken when
	 * that happens.
	 *
	 * This counter is used by the wait_seqno code to notice that reset
	 * event happened and it needs to restart the entire ioctl (since most
	 * likely the seqno it waited for won&apos;t ever signal anytime soon).
	 *
	 * This is important for lock-free wait paths, where no contended lock
	 * naturally enforces the correct ordering between the bail-out of the
	 * waiter and the gpu reset work code.
	 */</doc>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_gem.c' l='1357' u='a' c='__wait_seqno'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_gem.c' l='1357' u='a' c='__wait_seqno'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_gem.c' l='1357' u='a' c='__wait_seqno'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_gem.c' l='1357' u='a' c='__wait_seqno'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_gem.c' l='1357' u='a' c='__wait_seqno'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_gem.c' l='1357' u='a' c='__wait_seqno'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_gem.c' l='1547' u='a' c='i915_wait_seqno'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_gem.c' l='1623' u='a' c='i915_gem_object_wait_rendering__nonblocking'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_gem.c' l='3395' u='a' c='i915_gem_wait_ioctl'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_gem.c' l='4601' u='a' c='i915_gem_ring_throttle'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_gem.c' l='5329' u='a' c='i915_gem_entervt_ioctl'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_irq.c' l='2238' u='a' c='i915_error_work_func'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_irq.c' l='2245' u='a' c='i915_error_work_func'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_irq.c' l='2378' u='a' c='i915_handle_error'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='2452' u='a' c='intel_crtc_has_pending_flip'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='9031' u='a' c='intel_crtc_page_flip'/>
