<dec f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.h' l='201' type='__uint32_t'/>
<offset>96</offset>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='5092' u='w' c='i9xx_update_pll_dividers'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='5096' u='w' c='i9xx_update_pll_dividers'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='5891' u='w' c='i9xx_get_pipe_config'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='6654' u='w' c='ironlake_crtc_mode_set'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='6656' u='w' c='ironlake_crtc_mode_set'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='8250' u='r' c='i9xx_crtc_clock_get'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='8392' u='w' c='intel_crtc_mode_get'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='9741' u='r' c='intel_pipe_config_compare'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='9741' u='r' c='intel_pipe_config_compare'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='9741' u='r' c='intel_pipe_config_compare'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='9741' u='r' c='intel_pipe_config_compare'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='10535' u='w' c='ibx_pch_dpll_get_hw_state'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='10544' u='r' c='ibx_pch_dpll_mode_set'/>
