<dec f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/include/subdev/clock.h' l='72' type='int'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/device/nouveau_engine_device_ctrl.c' l='48' u='r' c='nouveau_control_mthd_pstate_info'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/device/nouveau_engine_device_ctrl.c' l='73' u='r' c='nouveau_control_mthd_pstate_attr'/>
<offset>2304</offset>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/subdev/clock/nouveau_subdev_clock_base.c' l='210' u='r' c='nouveau_pstate_calc'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/subdev/clock/nouveau_subdev_clock_base.c' l='212' u='r' c='nouveau_pstate_calc'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/subdev/clock/nouveau_subdev_clock_base.c' l='341' u='w' c='nouveau_pstate_new'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/subdev/clock/nouveau_subdev_clock_base.c' l='387' u='r' c='nouveau_clock_astate'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/subdev/clock/nouveau_subdev_clock_base.c' l='398' u='r' c='nouveau_clock_tstate'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/subdev/clock/nouveau_subdev_clock_base.c' l='407' u='r' c='nouveau_clock_dstate'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/subdev/clock/nouveau_subdev_clock_base.c' l='438' u='r' c='_nouveau_clock_init'/>
