<dec f='src/src/sys/external/bsd/drm2/dist/drm/radeon/radeon_mode.h' l='747' type='void radeon_compute_pll_avivo(struct radeon_pll * pll, u32 freq, u32 * dot_clock_p, u32 * fb_div_p, u32 * frac_fb_div_p, u32 * ref_div_p, u32 * post_div_p)'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/radeon/atombios_crtc.c' l='1051' u='c' c='atombios_crtc_set_pll'/>
<def f='src/src/sys/external/bsd/drm2/dist/drm/radeon/radeon_display.c' l='916' ll='1053' type='void radeon_compute_pll_avivo(struct radeon_pll * pll, u32 freq, u32 * dot_clock_p, u32 * fb_div_p, u32 * frac_fb_div_p, u32 * ref_div_p, u32 * post_div_p)'/>
<doc f='src/src/sys/external/bsd/drm2/dist/drm/radeon/radeon_display.c' l='903'>/**
 * radeon_compute_pll_avivo - compute PLL paramaters
 *
 * @pll: information about the PLL
 * @dot_clock_p: resulting pixel clock
 * fb_div_p: resulting feedback divider
 * frac_fb_div_p: fractional part of the feedback divider
 * ref_div_p: resulting reference divider
 * post_div_p: resulting reference divider
 *
 * Try to calculate the PLL parameters to generate the given frequency:
 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
 */</doc>
