<dec f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/fifo/nv04.h' l='136' type='unsigned int'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/fifo/nouveau_engine_fifo_nv04.c' l='169' u='r' c='nv04_fifo_chan_dtor'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/fifo/nouveau_engine_fifo_nv04.c' l='217' u='r' c='nv04_fifo_chan_fini'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/fifo/nouveau_engine_fifo_nv04.c' l='218' u='r' c='nv04_fifo_chan_fini'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/fifo/nouveau_engine_fifo_nv04.c' l='222' u='r' c='nv04_fifo_chan_fini'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/fifo/nouveau_engine_fifo_nv04.c' l='227' u='r' c='nv04_fifo_chan_fini'/>
<offset>0</offset>
