cad/py-MyHDL/../../cad/py-MyHDL/patches/patch-cosimulation_cver_Makefile.lnx: d4970d90cbabefb580e5ee5656de9ce29979b854eca3d51b5e6886db2dad7133
cad/py-MyHDL/DESCR: 74239894fcb8d636e769089899b54f0d5ae067daa1c7b940f27a53819012046f
cad/py-MyHDL/Makefile.common: 225c51b029d18e353ec9ae3231f124ca19f842ed7c78fa2e933321357c9197f7
cad/py-MyHDL/Makefile: 7ad6ae45d3a0116e6b77aa463a680c0168320bec538f8d459617a7dc950cdee9
cad/py-MyHDL/PLIST: 7df6b44c340723c6da240901d51929a97bcd49fd2d656306f9a7651fe341b79b
cad/py-MyHDL/distinfo: 69c5ea1dbac8188cf98e2d79d7c5d32a31b766ed61d5b516eed784ecc76d1e24
