require '_h2ph_pre.ph';

unless(defined(&_MAC68K_SCSI96REG_H_)) {
    eval 'sub _MAC68K_SCSI96REG_H_ () {1;}' unless defined(&_MAC68K_SCSI96REG_H_);
    eval 'sub PAD {
        local($x) = @_;
	    eval q(\'u_char\' $x [15];);
    }' unless defined(&PAD);
    eval 'sub sdidreg () { &statreg;}' unless defined(&sdidreg);
    eval 'sub stimreg () { &instreg;}' unless defined(&stimreg);
    eval 'sub soffsetreg () { &fifostatereg;}' unless defined(&soffsetreg);
    undef(&PAD) if defined(&PAD);
    eval 'sub NCR96_CTCREG () {0x0;}' unless defined(&NCR96_CTCREG);
    eval 'sub NCR96_STCREG () {0x0;}' unless defined(&NCR96_STCREG);
    eval 'sub NCR96_FFREG () {0x2;}' unless defined(&NCR96_FFREG);
    eval 'sub NCR96_CMDREG () {0x3;}' unless defined(&NCR96_CMDREG);
    eval 'sub NCR96_DMA () {0x80;}' unless defined(&NCR96_DMA);
    eval 'sub NCR96_CMD_INFOXFER () {0x10;}' unless defined(&NCR96_CMD_INFOXFER);
    eval 'sub NCR96_CMD_ICCS () {0x11;}' unless defined(&NCR96_CMD_ICCS);
    eval 'sub NCR96_CMD_MSGACC () {0x12;}' unless defined(&NCR96_CMD_MSGACC);
    eval 'sub NCR96_CMD_TPB () {0x18;}' unless defined(&NCR96_CMD_TPB);
    eval 'sub NCR96_CMD_SETATN () {0x1a;}' unless defined(&NCR96_CMD_SETATN);
    eval 'sub NCR96_CMD_RESETATN () {0x1b;}' unless defined(&NCR96_CMD_RESETATN);
    eval 'sub NCR96_CMD_RESEL () {0x40;}' unless defined(&NCR96_CMD_RESEL);
    eval 'sub NCR96_CMD_SEL () {0x41;}' unless defined(&NCR96_CMD_SEL);
    eval 'sub NCR96_CMD_SELATN () {0x42;}' unless defined(&NCR96_CMD_SELATN);
    eval 'sub NCR96_CMD_SELATNS () {0x43;}' unless defined(&NCR96_CMD_SELATNS);
    eval 'sub NCR96_CMD_ENSEL () {0x44;}' unless defined(&NCR96_CMD_ENSEL);
    eval 'sub NCR96_CMD_DISSEL () {0x45;}' unless defined(&NCR96_CMD_DISSEL);
    eval 'sub NCR96_CMD_SELATN3 () {0x46;}' unless defined(&NCR96_CMD_SELATN3);
    eval 'sub NCR96_CMD_NOOP () {0x00;}' unless defined(&NCR96_CMD_NOOP);
    eval 'sub NCR96_CMD_CLRFIFO () {0x01;}' unless defined(&NCR96_CMD_CLRFIFO);
    eval 'sub NCR96_CMD_RESETDEV () {0x02;}' unless defined(&NCR96_CMD_RESETDEV);
    eval 'sub NCR96_CMD_RESETBUS () {0x03;}' unless defined(&NCR96_CMD_RESETBUS);
    eval 'sub NCR96_STATREG () {0x4;}' unless defined(&NCR96_STATREG);
    eval 'sub NCR96_STAT_INT () {0x80;}' unless defined(&NCR96_STAT_INT);
    eval 'sub NCR96_STAT_IOE () {0x40;}' unless defined(&NCR96_STAT_IOE);
    eval 'sub NCR96_STAT_PE () {0x20;}' unless defined(&NCR96_STAT_PE);
    eval 'sub NCR96_STAT_CTZ () {0x10;}' unless defined(&NCR96_STAT_CTZ);
    eval 'sub NCR96_STAT_GCV () {0x08;}' unless defined(&NCR96_STAT_GCV);
    eval 'sub NCR96_STAT_PHASE () {0x07;}' unless defined(&NCR96_STAT_PHASE);
    eval 'sub NCR96_STAT_MSG () {0x04;}' unless defined(&NCR96_STAT_MSG);
    eval 'sub NCR96_STAT_CD () {0x02;}' unless defined(&NCR96_STAT_CD);
    eval 'sub NCR96_STAT_IO () {0x01;}' unless defined(&NCR96_STAT_IO);
    eval 'sub NCR96_SDIDREG () {0x4;}' unless defined(&NCR96_SDIDREG);
    eval 'sub NCR96_SDID_MASK () {0x07;}' unless defined(&NCR96_SDID_MASK);
    eval 'sub NCR96_INSTREG () {0x5;}' unless defined(&NCR96_INSTREG);
    eval 'sub NCR96_ISR_SRST () {0x80;}' unless defined(&NCR96_ISR_SRST);
    eval 'sub NCR96_ISR_INVAL () {0x40;}' unless defined(&NCR96_ISR_INVAL);
    eval 'sub NCR96_ISR_DISCONN () {0x20;}' unless defined(&NCR96_ISR_DISCONN);
    eval 'sub NCR96_ISR_SREQ () {0x10;}' unless defined(&NCR96_ISR_SREQ);
    eval 'sub NCR96_ISR_SO () {0x08;}' unless defined(&NCR96_ISR_SO);
    eval 'sub NCR96_ISR_RESEL () {0x04;}' unless defined(&NCR96_ISR_RESEL);
    eval 'sub NCR96_ISR_SELATN () {0x02;}' unless defined(&NCR96_ISR_SELATN);
    eval 'sub NCR96_ISR_SEL () {0x01;}' unless defined(&NCR96_ISR_SEL);
    eval 'sub NCR96_STIMREG () {0x5;}' unless defined(&NCR96_STIMREG);
    eval 'sub NCR96_ISREG () {0x6;}' unless defined(&NCR96_ISREG);
    eval 'sub NCR96_IS_MASK () {0x0f;}' unless defined(&NCR96_IS_MASK);
    eval 'sub NCR96_STPREG () {0x6;}' unless defined(&NCR96_STPREG);
    eval 'sub NCR96_STP_MASK () {0x1f;}' unless defined(&NCR96_STP_MASK);
    eval 'sub NCR96_CFISREG () {0x7;}' unless defined(&NCR96_CFISREG);
    eval 'sub NCR96_CF_MASK () {0x1f;}' unless defined(&NCR96_CF_MASK);
    eval 'sub NCR96_SOFREG () {0x7;}' unless defined(&NCR96_SOFREG);
    eval 'sub NCR96_SOF_MASK () {0x0f;}' unless defined(&NCR96_SOF_MASK);
    eval 'sub NCR96_CNTLREG1 () {0x8;}' unless defined(&NCR96_CNTLREG1);
    eval 'sub NCR96_C1_ETM () {0x80;}' unless defined(&NCR96_C1_ETM);
    eval 'sub NCR96_C1_DISR () {0x40;}' unless defined(&NCR96_C1_DISR);
    eval 'sub NCR96_C1_PTE () {0x20;}' unless defined(&NCR96_C1_PTE);
    eval 'sub NCR96_C1_PERE () {0x10;}' unless defined(&NCR96_C1_PERE);
    eval 'sub NCR96_C1_STE () {0x08;}' unless defined(&NCR96_C1_STE);
    eval 'sub NCR96_C1_SCSIID_MSK () {0x07;}' unless defined(&NCR96_C1_SCSIID_MSK);
    eval 'sub NCR96_CLKFREG () {0x9;}' unless defined(&NCR96_CLKFREG);
    eval 'sub NCR96_CLKF_MASK () {0x07;}' unless defined(&NCR96_CLKF_MASK);
    eval 'sub NCR96_FTMREG () {0xa;}' unless defined(&NCR96_FTMREG);
    eval 'sub NCR96_FTM_MASK () {0x07;}' unless defined(&NCR96_FTM_MASK);
    eval 'sub NCR96_CNTLREG2 () {0xb;}' unless defined(&NCR96_CNTLREG2);
    eval 'sub NCR96_C2_DAE () {0x80;}' unless defined(&NCR96_C2_DAE);
    eval 'sub NCR96_C2_LSP () {0x40;}' unless defined(&NCR96_C2_LSP);
    eval 'sub NCR96_C2_SBO () {0x20;}' unless defined(&NCR96_C2_SBO);
    eval 'sub NCR96_C2_TSDR () {0x10;}' unless defined(&NCR96_C2_TSDR);
    eval 'sub NCR96_C2_S2FE () {0x08;}' unless defined(&NCR96_C2_S2FE);
    eval 'sub NCR96_C2_ACDPE () {0x04;}' unless defined(&NCR96_C2_ACDPE);
    eval 'sub NCR96_C2_PGRP () {0x02;}' unless defined(&NCR96_C2_PGRP);
    eval 'sub NCR96_C2_PGDP () {0x01;}' unless defined(&NCR96_C2_PGDP);
    eval 'sub NCR96_CNTLREG3 () {0xc;}' unless defined(&NCR96_CNTLREG3);
    eval 'sub NCR96_C3_LBTM () {0x04;}' unless defined(&NCR96_C3_LBTM);
    eval 'sub NCR96_C3_MDM () {0x02;}' unless defined(&NCR96_C3_MDM);
    eval 'sub NCR96_C3_BS8 () {0x01;}' unless defined(&NCR96_C3_BS8);
    eval 'sub NCR96_DALREG () {0xf;}' unless defined(&NCR96_DALREG);
}
1;
