require '_h2ph_pre.ph';

unless(defined(&DISCONN)) {
    sub DISCONN () {	0x001;}
}
unless(defined(&DMA_IN_PROGRESS)) {
    sub DMA_IN_PROGRESS () {	0x002;}
}
unless(defined(&DMA_IN)) {
    sub DMA_IN () {	0x004;}
}
unless(defined(&DMA_RESUME)) {
    sub DMA_RESUME () {	0x08;}
}
unless(defined(&DMA_OUT)) {
    sub DMA_OUT () {	0x010;}
}
unless(defined(&DID_SYNC)) {
    sub DID_SYNC () {	0x020;}
}
unless(defined(&TRY_SYNC)) {
    sub TRY_SYNC () {	0x040;}
}
unless(defined(&PARITY_ERR)) {
    sub PARITY_ERR () {	0x080;}
}
unless(defined(&CHECK_SENSE)) {
    sub CHECK_SENSE () {	0x100;}
}
if(defined(&USE_NEW_SCSI)) {
}
unless(defined(&ASC_STATE_IDLE)) {
    sub ASC_STATE_IDLE () {	0;}
}
unless(defined(&ASC_STATE_BUSY)) {
    sub ASC_STATE_BUSY () {	1;}
}
unless(defined(&ASC_STATE_TARGET)) {
    sub ASC_STATE_TARGET () {	2;}
}
unless(defined(&ASC_STATE_RESEL)) {
    sub ASC_STATE_RESEL () {	3;}
}
unless(defined(&ASC_SPEED_25_MHZ)) {
    sub ASC_SPEED_25_MHZ () {	250;}
}
unless(defined(&ASC_SPEED_12_5_MHZ)) {
    sub ASC_SPEED_12_5_MHZ () {	125;}
}
unless(defined(&ASCDMA_READ)) {
    sub ASCDMA_READ () {	1;}
}
unless(defined(&ASCDMA_WRITE)) {
    sub ASCDMA_WRITE () {	2;}
}
1;
