require '_h2ph_pre.ph';

no warnings 'redefine';

unless(defined(&_DEV_PCI_PCIIDE_SII3112_REG_H_)) {
    eval 'sub _DEV_PCI_PCIIDE_SII3112_REG_H_ () {1;}' unless defined(&_DEV_PCI_PCIIDE_SII3112_REG_H_);
    eval 'sub SII3112_PCI_CFGCTL () {0x40;}' unless defined(&SII3112_PCI_CFGCTL);
    eval 'sub CFGCTL_CFGWREN () {(1 << 0);}' unless defined(&CFGCTL_CFGWREN);
    eval 'sub CFGCTL_BA5INDEN () {(1 << 1);}' unless defined(&CFGCTL_BA5INDEN);
    eval 'sub SII3112_PCI_SWDATA () {0x44;}' unless defined(&SII3112_PCI_SWDATA);
    eval 'sub SII3112_PCI_BM_IDE0 () {0x70;}' unless defined(&SII3112_PCI_BM_IDE0);
    eval 'sub SII3112_PCI_PRD_IDE0 () {0x74;}' unless defined(&SII3112_PCI_PRD_IDE0);
    eval 'sub SII3112_PCI_BM_IDE1 () {0x78;}' unless defined(&SII3112_PCI_BM_IDE1);
    eval 'sub SII3112_PCI_PRD_IDE1 () {0x7c;}' unless defined(&SII3112_PCI_PRD_IDE1);
    eval 'sub SII3112_DTM_IDE0 () {0x80;}' unless defined(&SII3112_DTM_IDE0);
    eval 'sub SII3112_DTM_IDE1 () {0x84;}' unless defined(&SII3112_DTM_IDE1);
    eval 'sub DTM_IDEx_PIO () {0x;}' unless defined(&DTM_IDEx_PIO);
    eval 'sub DTM_IDEx_DMA () {0x2;}' unless defined(&DTM_IDEx_DMA);
    eval 'sub SII3112_SCS_CMD () {0x88;}' unless defined(&SII3112_SCS_CMD);
    eval 'sub SCS_CMD_PBM_RESET () {(1 << 0);}' unless defined(&SCS_CMD_PBM_RESET);
    eval 'sub SCS_CMD_ARB_RESET () {(1 << 1);}' unless defined(&SCS_CMD_ARB_RESET);
    eval 'sub SCS_CMD_FF1_RESET () {(1 << 4);}' unless defined(&SCS_CMD_FF1_RESET);
    eval 'sub SCS_CMD_FF0_RESET () {(1 << 5);}' unless defined(&SCS_CMD_FF0_RESET);
    eval 'sub SCS_CMD_IDE1_RESET () {(1 << 6);}' unless defined(&SCS_CMD_IDE1_RESET);
    eval 'sub SCS_CMD_IDE0_RESET () {(1 << 7);}' unless defined(&SCS_CMD_IDE0_RESET);
    eval 'sub SCS_CMD_FF3_RESET () {(1 << 8);}' unless defined(&SCS_CMD_FF3_RESET);
    eval 'sub SCS_CMD_FF2_RESET () {(1 << 9);}' unless defined(&SCS_CMD_FF2_RESET);
    eval 'sub SCS_CMD_IDE3_RESET () {(1 << 10);}' unless defined(&SCS_CMD_IDE3_RESET);
    eval 'sub SCS_CMD_IDE2_RESET () {(1 << 11);}' unless defined(&SCS_CMD_IDE2_RESET);
    eval 'sub SCS_CMD_BA5_EN () {(1 << 16);}' unless defined(&SCS_CMD_BA5_EN);
    eval 'sub SCS_CMD_M66EN () {(1 << 16);}' unless defined(&SCS_CMD_M66EN);
    eval 'sub SCS_CMD_IDE0_INT_BLOCK () {(1 << 22);}' unless defined(&SCS_CMD_IDE0_INT_BLOCK);
    eval 'sub SCS_CMD_IDE1_INT_BLOCK () {(1 << 23);}' unless defined(&SCS_CMD_IDE1_INT_BLOCK);
    eval 'sub SCS_CMD_IDE2_INT_BLOCK () {(1 << 24);}' unless defined(&SCS_CMD_IDE2_INT_BLOCK);
    eval 'sub SCS_CMD_IDE3_INT_BLOCK () {(1 << 25);}' unless defined(&SCS_CMD_IDE3_INT_BLOCK);
    eval 'sub SII3112_SSDR () {0x8c;}' unless defined(&SII3112_SSDR);
    eval 'sub SII3112_FMA_CSR () {0x90;}' unless defined(&SII3112_FMA_CSR);
    eval 'sub SII3112_FM_DATA () {0x94;}' unless defined(&SII3112_FM_DATA);
    eval 'sub SII3112_EEA_CSR () {0x98;}' unless defined(&SII3112_EEA_CSR);
    eval 'sub SII3112_EE_DATA () {0x9c;}' unless defined(&SII3112_EE_DATA);
    eval 'sub SII3112_TCS_IDE0 () {0xa0;}' unless defined(&SII3112_TCS_IDE0);
    eval 'sub SII3112_TCS_IDE1 () {0xb0;}' unless defined(&SII3112_TCS_IDE1);
    eval 'sub TCS_IDEx_BCA () {(1 << 1);}' unless defined(&TCS_IDEx_BCA);
    eval 'sub TCS_IDEx_CH_RESET () {(1 << 2);}' unless defined(&TCS_IDEx_CH_RESET);
    eval 'sub TCS_IDEx_VDMA_INT () {(1 << 10);}' unless defined(&TCS_IDEx_VDMA_INT);
    eval 'sub TCS_IDEx_INT () {(1 << 11);}' unless defined(&TCS_IDEx_INT);
    eval 'sub TCS_IDEx_WTT () {(1 << 12);}' unless defined(&TCS_IDEx_WTT);
    eval 'sub TCS_IDEx_WTEN () {(1 << 13);}' unless defined(&TCS_IDEx_WTEN);
    eval 'sub TCS_IDEx_WTINTEN () {(1 << 14);}' unless defined(&TCS_IDEx_WTINTEN);
    eval 'sub SII3112_BA5_IND_ADDR () {0xc0;}' unless defined(&SII3112_BA5_IND_ADDR);
    eval 'sub SII3112_BA5_IND_DATA () {0xc4;}' unless defined(&SII3112_BA5_IND_DATA);
    eval 'sub ba5_SIS () {0x214;}' unless defined(&ba5_SIS);
    eval 'sub IDEDMA_CMD_INT_STEER () {(1 << 1);}' unless defined(&IDEDMA_CMD_INT_STEER);
    eval 'sub BA5_READ_4 {
        my($sc, $chan, $reg) = @_;
	    eval q( &ba5_read_4(($sc),  ($satalink_ba5_regmap[&(chan)]->{reg})));
    }' unless defined(&BA5_READ_4);
    eval 'sub BA5_WRITE_4 {
        my($sc, $chan, $reg, $val) = @_;
	    eval q( &ba5_write_4(($sc),  ($satalink_ba5_regmap[&(chan)]->{reg}), ($val)));
    }' unless defined(&BA5_WRITE_4);
}
1;
