require '_h2ph_pre.ph';

no warnings 'redefine';

unless(defined(&PCIC_IOSIZE)) {
    sub PCIC_IOSIZE () {	2;}
}
unless(defined(&PCIC_REG_INDEX)) {
    sub PCIC_REG_INDEX () {	0;}
}
unless(defined(&PCIC_REG_DATA)) {
    sub PCIC_REG_DATA () {	1;}
}
unless(defined(&PCIC_CHIP0_BASE)) {
    sub PCIC_CHIP0_BASE () {	0x;}
}
unless(defined(&PCIC_CHIP1_BASE)) {
    sub PCIC_CHIP1_BASE () {	0x80;}
}
unless(defined(&PCIC_SOCKETA_INDEX)) {
    sub PCIC_SOCKETA_INDEX () {	0x;}
}
unless(defined(&PCIC_SOCKETB_INDEX)) {
    sub PCIC_SOCKETB_INDEX () {	0x40;}
}
unless(defined(&PCIC_IDENT)) {
    sub PCIC_IDENT () {	0x;}
}
unless(defined(&PCIC_IDENT_IFTYPE_MASK)) {
    sub PCIC_IDENT_IFTYPE_MASK () {	0xc0;}
}
unless(defined(&PCIC_IDENT_IFTYPE_IO_ONLY)) {
    sub PCIC_IDENT_IFTYPE_IO_ONLY () {	0x;}
}
unless(defined(&PCIC_IDENT_IFTYPE_MEM_ONLY)) {
    sub PCIC_IDENT_IFTYPE_MEM_ONLY () {	0x40;}
}
unless(defined(&PCIC_IDENT_IFTYPE_MEM_AND_IO)) {
    sub PCIC_IDENT_IFTYPE_MEM_AND_IO () {	0x80;}
}
unless(defined(&PCIC_IDENT_IFTYPE_RESERVED)) {
    sub PCIC_IDENT_IFTYPE_RESERVED () {	0xc0;}
}
unless(defined(&PCIC_IDENT_ZERO)) {
    sub PCIC_IDENT_ZERO () {	0x30;}
}
unless(defined(&PCIC_IDENT_REV_MASK)) {
    sub PCIC_IDENT_REV_MASK () {	0xf;}
}
unless(defined(&PCIC_IDENT_REV_I82365SLR0)) {
    sub PCIC_IDENT_REV_I82365SLR0 () {	0x82;}
}
unless(defined(&PCIC_IDENT_REV_I82365SLR1)) {
    sub PCIC_IDENT_REV_I82365SLR1 () {	0x83;}
}
unless(defined(&PCIC_IDENT_REV_I82365SLR2)) {
    sub PCIC_IDENT_REV_I82365SLR2 () {	0x84;}
}
unless(defined(&PCIC_IF_STATUS)) {
    sub PCIC_IF_STATUS () {	0x1;}
}
unless(defined(&PCIC_IF_STATUS_GPI)) {
    sub PCIC_IF_STATUS_GPI () {	0x80;}
}
unless(defined(&PCIC_IF_STATUS_POWERACTIVE)) {
    sub PCIC_IF_STATUS_POWERACTIVE () {	0x40;}
}
unless(defined(&PCIC_IF_STATUS_READY)) {
    sub PCIC_IF_STATUS_READY () {	0x20;}
}
unless(defined(&PCIC_IF_STATUS_MEM_WP)) {
    sub PCIC_IF_STATUS_MEM_WP () {	0x10;}
}
unless(defined(&PCIC_IF_STATUS_CARDDETECT_MASK)) {
    sub PCIC_IF_STATUS_CARDDETECT_MASK () {	0xc;}
}
unless(defined(&PCIC_IF_STATUS_CARDDETECT_PRESENT)) {
    sub PCIC_IF_STATUS_CARDDETECT_PRESENT () {	0xc;}
}
unless(defined(&PCIC_IF_STATUS_BATTERY_MASK)) {
    sub PCIC_IF_STATUS_BATTERY_MASK () {	0x3;}
}
unless(defined(&PCIC_IF_STATUS_BATTERY_DEAD1)) {
    sub PCIC_IF_STATUS_BATTERY_DEAD1 () {	0x;}
}
unless(defined(&PCIC_IF_STATUS_BATTERY_DEAD2)) {
    sub PCIC_IF_STATUS_BATTERY_DEAD2 () {	0x1;}
}
unless(defined(&PCIC_IF_STATUS_BATTERY_WARNING)) {
    sub PCIC_IF_STATUS_BATTERY_WARNING () {	0x2;}
}
unless(defined(&PCIC_IF_STATUS_BATTERY_GOOD)) {
    sub PCIC_IF_STATUS_BATTERY_GOOD () {	0x3;}
}
unless(defined(&PCIC_PWRCTL)) {
    sub PCIC_PWRCTL () {	0x2;}
}
unless(defined(&PCIC_PWRCTL_OE)) {
    sub PCIC_PWRCTL_OE () {	0x80;}
}
unless(defined(&PCIC_PWRCTL_DISABLE_RESETDRV)) {
    sub PCIC_PWRCTL_DISABLE_RESETDRV () {	0x40;}
}
unless(defined(&PCIC_PWRCTL_AUTOSWITCH_ENABLE)) {
    sub PCIC_PWRCTL_AUTOSWITCH_ENABLE () {	0x20;}
}
unless(defined(&PCIC_PWRCTL_PWR_ENABLE)) {
    sub PCIC_PWRCTL_PWR_ENABLE () {	0x10;}
}
unless(defined(&PCIC_PWRCTL_VPP2_MASK)) {
    sub PCIC_PWRCTL_VPP2_MASK () {	0xc;}
}
unless(defined(&PCIC_PWRCTL_VPP2_RESERVED)) {
    sub PCIC_PWRCTL_VPP2_RESERVED () {	0xc;}
}
unless(defined(&PCIC_PWRCTL_VPP2_EN1)) {
    sub PCIC_PWRCTL_VPP2_EN1 () {	0x8;}
}
unless(defined(&PCIC_PWRCTL_VPP2_EN0)) {
    sub PCIC_PWRCTL_VPP2_EN0 () {	0x4;}
}
unless(defined(&PCIC_PWRCTL_VPP2_ENX)) {
    sub PCIC_PWRCTL_VPP2_ENX () {	0x;}
}
unless(defined(&PCIC_PWRCTL_VPP1_MASK)) {
    sub PCIC_PWRCTL_VPP1_MASK () {	0x3;}
}
unless(defined(&PCIC_PWRCTL_VPP1_RESERVED)) {
    sub PCIC_PWRCTL_VPP1_RESERVED () {	0x3;}
}
unless(defined(&PCIC_PWRCTL_VPP1_EN1)) {
    sub PCIC_PWRCTL_VPP1_EN1 () {	0x2;}
}
unless(defined(&PCIC_PWRCTL_VPP1_EN0)) {
    sub PCIC_PWRCTL_VPP1_EN0 () {	0x1;}
}
unless(defined(&PCIC_PWRCTL_VPP1_ENX)) {
    sub PCIC_PWRCTL_VPP1_ENX () {	0x;}
}
unless(defined(&PCIC_CSC)) {
    sub PCIC_CSC () {	0x4;}
}
unless(defined(&PCIC_CSC_ZERO)) {
    sub PCIC_CSC_ZERO () {	0xe0;}
}
unless(defined(&PCIC_CSC_GPI)) {
    sub PCIC_CSC_GPI () {	0x10;}
}
unless(defined(&PCIC_CSC_CD)) {
    sub PCIC_CSC_CD () {	0x8;}
}
unless(defined(&PCIC_CSC_READY)) {
    sub PCIC_CSC_READY () {	0x4;}
}
unless(defined(&PCIC_CSC_BATTWARN)) {
    sub PCIC_CSC_BATTWARN () {	0x2;}
}
unless(defined(&PCIC_CSC_BATTDEAD)) {
    sub PCIC_CSC_BATTDEAD () {	0x1;}
}
unless(defined(&PCIC_CSC_RI)) {
    sub PCIC_CSC_RI () {	0x1;}
}
unless(defined(&PCIC_ADDRWIN_ENABLE)) {
    sub PCIC_ADDRWIN_ENABLE () {	0x6;}
}
unless(defined(&PCIC_ADDRWIN_ENABLE_IO1)) {
    sub PCIC_ADDRWIN_ENABLE_IO1 () {	0x80;}
}
unless(defined(&PCIC_ADDRWIN_ENABLE_IO0)) {
    sub PCIC_ADDRWIN_ENABLE_IO0 () {	0x40;}
}
unless(defined(&PCIC_ADDRWIN_ENABLE_MEMCS16)) {
    sub PCIC_ADDRWIN_ENABLE_MEMCS16 () {	0x20;}
}
unless(defined(&PCIC_ADDRWIN_ENABLE_MEM4)) {
    sub PCIC_ADDRWIN_ENABLE_MEM4 () {	0x10;}
}
unless(defined(&PCIC_ADDRWIN_ENABLE_MEM3)) {
    sub PCIC_ADDRWIN_ENABLE_MEM3 () {	0x8;}
}
unless(defined(&PCIC_ADDRWIN_ENABLE_MEM2)) {
    sub PCIC_ADDRWIN_ENABLE_MEM2 () {	0x4;}
}
unless(defined(&PCIC_ADDRWIN_ENABLE_MEM1)) {
    sub PCIC_ADDRWIN_ENABLE_MEM1 () {	0x2;}
}
unless(defined(&PCIC_ADDRWIN_ENABLE_MEM0)) {
    sub PCIC_ADDRWIN_ENABLE_MEM0 () {	0x1;}
}
unless(defined(&PCIC_CARD_DETECT)) {
    sub PCIC_CARD_DETECT () {	0x16;}
}
unless(defined(&PCIC_CARD_DETECT_RESERVED)) {
    sub PCIC_CARD_DETECT_RESERVED () {	0xc0;}
}
unless(defined(&PCIC_CARD_DETECT_SW_INTR)) {
    sub PCIC_CARD_DETECT_SW_INTR () {	0x20;}
}
unless(defined(&PCIC_CARD_DETECT_RESUME_ENABLE)) {
    sub PCIC_CARD_DETECT_RESUME_ENABLE () {	0x10;}
}
unless(defined(&PCIC_CARD_DETECT_GPI_TRANSCTL)) {
    sub PCIC_CARD_DETECT_GPI_TRANSCTL () {	0x8;}
}
unless(defined(&PCIC_CARD_DETECT_GPI_ENABLE)) {
    sub PCIC_CARD_DETECT_GPI_ENABLE () {	0x4;}
}
unless(defined(&PCIC_CARD_DETECT_CFGRST_ENABLE)) {
    sub PCIC_CARD_DETECT_CFGRST_ENABLE () {	0x2;}
}
unless(defined(&PCIC_CARD_DETECT_MEMDLY_INHIBIT)) {
    sub PCIC_CARD_DETECT_MEMDLY_INHIBIT () {	0x1;}
}
unless(defined(&PCIC_INTR)) {
    sub PCIC_INTR () {	0x3;}
}
unless(defined(&PCIC_INTR_RI_ENABLE)) {
    sub PCIC_INTR_RI_ENABLE () {	0x80;}
}
unless(defined(&PCIC_INTR_RESET)) {
    sub PCIC_INTR_RESET () {	0x40;}
}
unless(defined(&PCIC_INTR_CARDTYPE_MASK)) {
    sub PCIC_INTR_CARDTYPE_MASK () {	0x20;}
}
unless(defined(&PCIC_INTR_CARDTYPE_IO)) {
    sub PCIC_INTR_CARDTYPE_IO () {	0x20;}
}
unless(defined(&PCIC_INTR_CARDTYPE_MEM)) {
    sub PCIC_INTR_CARDTYPE_MEM () {	0x;}
}
unless(defined(&PCIC_INTR_ENABLE)) {
    sub PCIC_INTR_ENABLE () {	0x10;}
}
unless(defined(&PCIC_INTR_IRQ_MASK)) {
    sub PCIC_INTR_IRQ_MASK () {	0xf;}
}
unless(defined(&PCIC_INTR_IRQ_SHIFT)) {
    sub PCIC_INTR_IRQ_SHIFT () {	0;}
}
unless(defined(&PCIC_INTR_IRQ_NONE)) {
    sub PCIC_INTR_IRQ_NONE () {	0x;}
}
unless(defined(&PCIC_INTR_IRQ_RESERVED1)) {
    sub PCIC_INTR_IRQ_RESERVED1 () {	0x1;}
}
unless(defined(&PCIC_INTR_IRQ_RESERVED2)) {
    sub PCIC_INTR_IRQ_RESERVED2 () {	0x2;}
}
unless(defined(&PCIC_INTR_IRQ3)) {
    sub PCIC_INTR_IRQ3 () {	0x3;}
}
unless(defined(&PCIC_INTR_IRQ4)) {
    sub PCIC_INTR_IRQ4 () {	0x4;}
}
unless(defined(&PCIC_INTR_IRQ5)) {
    sub PCIC_INTR_IRQ5 () {	0x5;}
}
unless(defined(&PCIC_INTR_IRQ_RESERVED6)) {
    sub PCIC_INTR_IRQ_RESERVED6 () {	0x6;}
}
unless(defined(&PCIC_INTR_IRQ7)) {
    sub PCIC_INTR_IRQ7 () {	0x7;}
}
unless(defined(&PCIC_INTR_IRQ_RESERVED8)) {
    sub PCIC_INTR_IRQ_RESERVED8 () {	0x8;}
}
unless(defined(&PCIC_INTR_IRQ9)) {
    sub PCIC_INTR_IRQ9 () {	0x9;}
}
unless(defined(&PCIC_INTR_IRQ10)) {
    sub PCIC_INTR_IRQ10 () {	0xa;}
}
unless(defined(&PCIC_INTR_IRQ11)) {
    sub PCIC_INTR_IRQ11 () {	0xb;}
}
unless(defined(&PCIC_INTR_IRQ12)) {
    sub PCIC_INTR_IRQ12 () {	0xc;}
}
unless(defined(&PCIC_INTR_IRQ_RESERVED13)) {
    sub PCIC_INTR_IRQ_RESERVED13 () {	0xd;}
}
unless(defined(&PCIC_INTR_IRQ14)) {
    sub PCIC_INTR_IRQ14 () {	0xe;}
}
unless(defined(&PCIC_INTR_IRQ15)) {
    sub PCIC_INTR_IRQ15 () {	0xf;}
}
unless(defined(&PCIC_INTR_IRQ_VALIDMASK)) {
    sub PCIC_INTR_IRQ_VALIDMASK () {	0xdeb8;}
}
unless(defined(&PCIC_CSC_INTR)) {
    sub PCIC_CSC_INTR () {	0x5;}
}
unless(defined(&PCIC_CSC_INTR_IRQ_MASK)) {
    sub PCIC_CSC_INTR_IRQ_MASK () {	0xf0;}
}
unless(defined(&PCIC_CSC_INTR_IRQ_SHIFT)) {
    sub PCIC_CSC_INTR_IRQ_SHIFT () {	4;}
}
unless(defined(&PCIC_CSC_INTR_IRQ_NONE)) {
    sub PCIC_CSC_INTR_IRQ_NONE () {	0x;}
}
unless(defined(&PCIC_CSC_INTR_IRQ_RESERVED1)) {
    sub PCIC_CSC_INTR_IRQ_RESERVED1 () {	0x10;}
}
unless(defined(&PCIC_CSC_INTR_IRQ_RESERVED2)) {
    sub PCIC_CSC_INTR_IRQ_RESERVED2 () {	0x20;}
}
unless(defined(&PCIC_CSC_INTR_IRQ3)) {
    sub PCIC_CSC_INTR_IRQ3 () {	0x30;}
}
unless(defined(&PCIC_CSC_INTR_IRQ4)) {
    sub PCIC_CSC_INTR_IRQ4 () {	0x40;}
}
unless(defined(&PCIC_CSC_INTR_IRQ5)) {
    sub PCIC_CSC_INTR_IRQ5 () {	0x50;}
}
unless(defined(&PCIC_CSC_INTR_IRQ_RESERVED6)) {
    sub PCIC_CSC_INTR_IRQ_RESERVED6 () {	0x60;}
}
unless(defined(&PCIC_CSC_INTR_IRQ7)) {
    sub PCIC_CSC_INTR_IRQ7 () {	0x70;}
}
unless(defined(&PCIC_CSC_INTR_IRQ_RESERVED8)) {
    sub PCIC_CSC_INTR_IRQ_RESERVED8 () {	0x80;}
}
unless(defined(&PCIC_CSC_INTR_IRQ9)) {
    sub PCIC_CSC_INTR_IRQ9 () {	0x90;}
}
unless(defined(&PCIC_CSC_INTR_IRQ10)) {
    sub PCIC_CSC_INTR_IRQ10 () {	0xa0;}
}
unless(defined(&PCIC_CSC_INTR_IRQ11)) {
    sub PCIC_CSC_INTR_IRQ11 () {	0xb0;}
}
unless(defined(&PCIC_CSC_INTR_IRQ12)) {
    sub PCIC_CSC_INTR_IRQ12 () {	0xc0;}
}
unless(defined(&PCIC_CSC_INTR_IRQ_RESERVED13)) {
    sub PCIC_CSC_INTR_IRQ_RESERVED13 () {	0xd0;}
}
unless(defined(&PCIC_CSC_INTR_IRQ14)) {
    sub PCIC_CSC_INTR_IRQ14 () {	0xe0;}
}
unless(defined(&PCIC_CSC_INTR_IRQ15)) {
    sub PCIC_CSC_INTR_IRQ15 () {	0xf0;}
}
unless(defined(&PCIC_CSC_INTR_CD_ENABLE)) {
    sub PCIC_CSC_INTR_CD_ENABLE () {	0x8;}
}
unless(defined(&PCIC_CSC_INTR_READY_ENABLE)) {
    sub PCIC_CSC_INTR_READY_ENABLE () {	0x4;}
}
unless(defined(&PCIC_CSC_INTR_BATTWARN_ENABLE)) {
    sub PCIC_CSC_INTR_BATTWARN_ENABLE () {	0x2;}
}
unless(defined(&PCIC_CSC_INTR_BATTDEAD_ENABLE)) {
    sub PCIC_CSC_INTR_BATTDEAD_ENABLE () {	0x1;}
}
unless(defined(&PCIC_CSC_INTR_RI_ENABLE)) {
    sub PCIC_CSC_INTR_RI_ENABLE () {	0x1;}
}
unless(defined(&PCIC_CSC_INTR_IRQ_VALIDMASK)) {
    sub PCIC_CSC_INTR_IRQ_VALIDMASK () {	0xdeb8;}
}
unless(defined(&PCIC_IO_WINS)) {
    sub PCIC_IO_WINS () {	2;}
}
unless(defined(&PCIC_IOCTL)) {
    sub PCIC_IOCTL () {	0x7;}
}
unless(defined(&PCIC_IOCTL_IO1_WAITSTATE)) {
    sub PCIC_IOCTL_IO1_WAITSTATE () {	0x80;}
}
unless(defined(&PCIC_IOCTL_IO1_ZEROWAIT)) {
    sub PCIC_IOCTL_IO1_ZEROWAIT () {	0x40;}
}
unless(defined(&PCIC_IOCTL_IO1_IOCS16SRC_MASK)) {
    sub PCIC_IOCTL_IO1_IOCS16SRC_MASK () {	0x20;}
}
unless(defined(&PCIC_IOCTL_IO1_IOCS16SRC_CARD)) {
    sub PCIC_IOCTL_IO1_IOCS16SRC_CARD () {	0x20;}
}
unless(defined(&PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE)) {
    sub PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE () {	0x;}
}
unless(defined(&PCIC_IOCTL_IO1_DATASIZE_MASK)) {
    sub PCIC_IOCTL_IO1_DATASIZE_MASK () {	0x10;}
}
unless(defined(&PCIC_IOCTL_IO1_DATASIZE_16BIT)) {
    sub PCIC_IOCTL_IO1_DATASIZE_16BIT () {	0x10;}
}
unless(defined(&PCIC_IOCTL_IO1_DATASIZE_8BIT)) {
    sub PCIC_IOCTL_IO1_DATASIZE_8BIT () {	0x;}
}
unless(defined(&PCIC_IOCTL_IO0_WAITSTATE)) {
    sub PCIC_IOCTL_IO0_WAITSTATE () {	0x8;}
}
unless(defined(&PCIC_IOCTL_IO0_ZEROWAIT)) {
    sub PCIC_IOCTL_IO0_ZEROWAIT () {	0x4;}
}
unless(defined(&PCIC_IOCTL_IO0_IOCS16SRC_MASK)) {
    sub PCIC_IOCTL_IO0_IOCS16SRC_MASK () {	0x2;}
}
unless(defined(&PCIC_IOCTL_IO0_IOCS16SRC_CARD)) {
    sub PCIC_IOCTL_IO0_IOCS16SRC_CARD () {	0x2;}
}
unless(defined(&PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE)) {
    sub PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE () {	0x;}
}
unless(defined(&PCIC_IOCTL_IO0_DATASIZE_MASK)) {
    sub PCIC_IOCTL_IO0_DATASIZE_MASK () {	0x1;}
}
unless(defined(&PCIC_IOCTL_IO0_DATASIZE_16BIT)) {
    sub PCIC_IOCTL_IO0_DATASIZE_16BIT () {	0x1;}
}
unless(defined(&PCIC_IOCTL_IO0_DATASIZE_8BIT)) {
    sub PCIC_IOCTL_IO0_DATASIZE_8BIT () {	0x;}
}
unless(defined(&PCIC_IOADDR0_START_LSB)) {
    sub PCIC_IOADDR0_START_LSB () {	0x8;}
}
unless(defined(&PCIC_IOADDR0_START_MSB)) {
    sub PCIC_IOADDR0_START_MSB () {	0x9;}
}
unless(defined(&PCIC_IOADDR0_STOP_LSB)) {
    sub PCIC_IOADDR0_STOP_LSB () {	0xa;}
}
unless(defined(&PCIC_IOADDR0_STOP_MSB)) {
    sub PCIC_IOADDR0_STOP_MSB () {	0xb;}
}
unless(defined(&PCIC_IOADDR1_START_LSB)) {
    sub PCIC_IOADDR1_START_LSB () {	0xc;}
}
unless(defined(&PCIC_IOADDR1_START_MSB)) {
    sub PCIC_IOADDR1_START_MSB () {	0xd;}
}
unless(defined(&PCIC_IOADDR1_STOP_LSB)) {
    sub PCIC_IOADDR1_STOP_LSB () {	0xe;}
}
unless(defined(&PCIC_IOADDR1_STOP_MSB)) {
    sub PCIC_IOADDR1_STOP_MSB () {	0xf;}
}
unless(defined(&PCIC_MEM_WINS)) {
    sub PCIC_MEM_WINS () {	5;}
}
unless(defined(&PCIC_MEM_SHIFT)) {
    sub PCIC_MEM_SHIFT () {	12;}
}
unless(defined(&PCIC_MEM_PAGESIZE)) {
    sub PCIC_MEM_PAGESIZE () {	(1<< &PCIC_MEM_SHIFT);}
}
unless(defined(&PCIC_SYSMEM_ADDRX_SHIFT)) {
    sub PCIC_SYSMEM_ADDRX_SHIFT () {	 &PCIC_MEM_SHIFT;}
}
unless(defined(&PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_MASK)) {
    sub PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_MASK () {	0x80;}
}
unless(defined(&PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT)) {
    sub PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT () {	0x80;}
}
unless(defined(&PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_8BIT)) {
    sub PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_8BIT () {	0x;}
}
unless(defined(&PCIC_SYSMEM_ADDRX_START_MSB_ZEROWAIT)) {
    sub PCIC_SYSMEM_ADDRX_START_MSB_ZEROWAIT () {	0x40;}
}
unless(defined(&PCIC_SYSMEM_ADDRX_START_MSB_SCRATCH_MASK)) {
    sub PCIC_SYSMEM_ADDRX_START_MSB_SCRATCH_MASK () {	0x30;}
}
unless(defined(&PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK)) {
    sub PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK () {	0xf;}
}
unless(defined(&PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT_MASK)) {
    sub PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT_MASK () {	0xc0;}
}
unless(defined(&PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT0)) {
    sub PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT0 () {	0x;}
}
unless(defined(&PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT1)) {
    sub PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT1 () {	0x40;}
}
unless(defined(&PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2)) {
    sub PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2 () {	0x80;}
}
unless(defined(&PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT3)) {
    sub PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT3 () {	0xc0;}
}
unless(defined(&PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK)) {
    sub PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK () {	0xf;}
}
unless(defined(&PCIC_CARDMEM_ADDRX_SHIFT)) {
    sub PCIC_CARDMEM_ADDRX_SHIFT () {	 &PCIC_MEM_SHIFT;}
}
unless(defined(&PCIC_CARDMEM_ADDRX_MSB_WP)) {
    sub PCIC_CARDMEM_ADDRX_MSB_WP () {	0x80;}
}
unless(defined(&PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_MASK)) {
    sub PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_MASK () {	0x40;}
}
unless(defined(&PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR)) {
    sub PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR () {	0x40;}
}
unless(defined(&PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_COMMON)) {
    sub PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_COMMON () {	0x;}
}
unless(defined(&PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK)) {
    sub PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK () {	0x3f;}
}
unless(defined(&PCIC_SYSMEM_ADDR0_START_LSB)) {
    sub PCIC_SYSMEM_ADDR0_START_LSB () {	0x10;}
}
unless(defined(&PCIC_SYSMEM_ADDR0_START_MSB)) {
    sub PCIC_SYSMEM_ADDR0_START_MSB () {	0x11;}
}
unless(defined(&PCIC_SYSMEM_ADDR0_STOP_LSB)) {
    sub PCIC_SYSMEM_ADDR0_STOP_LSB () {	0x12;}
}
unless(defined(&PCIC_SYSMEM_ADDR0_STOP_MSB)) {
    sub PCIC_SYSMEM_ADDR0_STOP_MSB () {	0x13;}
}
unless(defined(&PCIC_CARDMEM_ADDR0_LSB)) {
    sub PCIC_CARDMEM_ADDR0_LSB () {	0x14;}
}
unless(defined(&PCIC_CARDMEM_ADDR0_MSB)) {
    sub PCIC_CARDMEM_ADDR0_MSB () {	0x15;}
}
unless(defined(&PCIC_SYSMEM_ADDR1_START_LSB)) {
    sub PCIC_SYSMEM_ADDR1_START_LSB () {	0x18;}
}
unless(defined(&PCIC_SYSMEM_ADDR1_START_MSB)) {
    sub PCIC_SYSMEM_ADDR1_START_MSB () {	0x19;}
}
unless(defined(&PCIC_SYSMEM_ADDR1_STOP_LSB)) {
    sub PCIC_SYSMEM_ADDR1_STOP_LSB () {	0x1a;}
}
unless(defined(&PCIC_SYSMEM_ADDR1_STOP_MSB)) {
    sub PCIC_SYSMEM_ADDR1_STOP_MSB () {	0x1b;}
}
unless(defined(&PCIC_CARDMEM_ADDR1_LSB)) {
    sub PCIC_CARDMEM_ADDR1_LSB () {	0x1c;}
}
unless(defined(&PCIC_CARDMEM_ADDR1_MSB)) {
    sub PCIC_CARDMEM_ADDR1_MSB () {	0x1d;}
}
unless(defined(&PCIC_SYSMEM_ADDR2_START_LSB)) {
    sub PCIC_SYSMEM_ADDR2_START_LSB () {	0x20;}
}
unless(defined(&PCIC_SYSMEM_ADDR2_START_MSB)) {
    sub PCIC_SYSMEM_ADDR2_START_MSB () {	0x21;}
}
unless(defined(&PCIC_SYSMEM_ADDR2_STOP_LSB)) {
    sub PCIC_SYSMEM_ADDR2_STOP_LSB () {	0x22;}
}
unless(defined(&PCIC_SYSMEM_ADDR2_STOP_MSB)) {
    sub PCIC_SYSMEM_ADDR2_STOP_MSB () {	0x23;}
}
unless(defined(&PCIC_CARDMEM_ADDR2_LSB)) {
    sub PCIC_CARDMEM_ADDR2_LSB () {	0x24;}
}
unless(defined(&PCIC_CARDMEM_ADDR2_MSB)) {
    sub PCIC_CARDMEM_ADDR2_MSB () {	0x25;}
}
unless(defined(&PCIC_SYSMEM_ADDR3_START_LSB)) {
    sub PCIC_SYSMEM_ADDR3_START_LSB () {	0x28;}
}
unless(defined(&PCIC_SYSMEM_ADDR3_START_MSB)) {
    sub PCIC_SYSMEM_ADDR3_START_MSB () {	0x29;}
}
unless(defined(&PCIC_SYSMEM_ADDR3_STOP_LSB)) {
    sub PCIC_SYSMEM_ADDR3_STOP_LSB () {	0x2a;}
}
unless(defined(&PCIC_SYSMEM_ADDR3_STOP_MSB)) {
    sub PCIC_SYSMEM_ADDR3_STOP_MSB () {	0x2b;}
}
unless(defined(&PCIC_CARDMEM_ADDR3_LSB)) {
    sub PCIC_CARDMEM_ADDR3_LSB () {	0x2c;}
}
unless(defined(&PCIC_CARDMEM_ADDR3_MSB)) {
    sub PCIC_CARDMEM_ADDR3_MSB () {	0x2d;}
}
unless(defined(&PCIC_SYSMEM_ADDR4_START_LSB)) {
    sub PCIC_SYSMEM_ADDR4_START_LSB () {	0x30;}
}
unless(defined(&PCIC_SYSMEM_ADDR4_START_MSB)) {
    sub PCIC_SYSMEM_ADDR4_START_MSB () {	0x31;}
}
unless(defined(&PCIC_SYSMEM_ADDR4_STOP_LSB)) {
    sub PCIC_SYSMEM_ADDR4_STOP_LSB () {	0x32;}
}
unless(defined(&PCIC_SYSMEM_ADDR4_STOP_MSB)) {
    sub PCIC_SYSMEM_ADDR4_STOP_MSB () {	0x33;}
}
unless(defined(&PCIC_CARDMEM_ADDR4_LSB)) {
    sub PCIC_CARDMEM_ADDR4_LSB () {	0x34;}
}
unless(defined(&PCIC_CARDMEM_ADDR4_MSB)) {
    sub PCIC_CARDMEM_ADDR4_MSB () {	0x35;}
}
unless(defined(&PCIC_INTEL_GLOBAL_CTL)) {
    sub PCIC_INTEL_GLOBAL_CTL () {	0x1e;}
}
unless(defined(&PCIC_INTEL_GLOBAL_CTL_RESERVED)) {
    sub PCIC_INTEL_GLOBAL_CTL_RESERVED () {	0xf0;}
}
unless(defined(&PCIC_INTEL_GLOBAL_CTL_IRQ14PULSE_ENABLE)) {
    sub PCIC_INTEL_GLOBAL_CTL_IRQ14PULSE_ENABLE () {	0x8;}
}
unless(defined(&PCIC_INTEL_GLOBAL_CTL_EXPLICIT_CSC_ACK)) {
    sub PCIC_INTEL_GLOBAL_CTL_EXPLICIT_CSC_ACK () {	0x4;}
}
unless(defined(&PCIC_INTEL_GLOBAL_CTL_IRQLEVEL_ENABLE)) {
    sub PCIC_INTEL_GLOBAL_CTL_IRQLEVEL_ENABLE () {	0x2;}
}
unless(defined(&PCIC_INTEL_GLOBAL_CTL_POWERDOWN)) {
    sub PCIC_INTEL_GLOBAL_CTL_POWERDOWN () {	0x1;}
}
unless(defined(&PCIC_CIRRUS_MISC_CTL_2)) {
    sub PCIC_CIRRUS_MISC_CTL_2 () {	0x1e;}
}
unless(defined(&PCIC_CIRRUS_MISC_CTL_2_SUSPEND)) {
    sub PCIC_CIRRUS_MISC_CTL_2_SUSPEND () {	0x4;}
}
unless(defined(&PCIC_CIRRUS_CHIP_INFO)) {
    sub PCIC_CIRRUS_CHIP_INFO () {	0x1f;}
}
unless(defined(&PCIC_CIRRUS_CHIP_INFO_CHIP_ID)) {
    sub PCIC_CIRRUS_CHIP_INFO_CHIP_ID () {	0xc0;}
}
unless(defined(&PCIC_CIRRUS_CHIP_INFO_SLOTS)) {
    sub PCIC_CIRRUS_CHIP_INFO_SLOTS () {	0x20;}
}
unless(defined(&PCIC_CIRRUS_CHIP_INFO_REV)) {
    sub PCIC_CIRRUS_CHIP_INFO_REV () {	0x1f;}
}
unless(defined(&PCIC_CIRRUS_EXTENDED_INDEX)) {
    sub PCIC_CIRRUS_EXTENDED_INDEX () {	0x2e;}
}
unless(defined(&PCIC_CIRRUS_EXTENDED_DATA)) {
    sub PCIC_CIRRUS_EXTENDED_DATA () {	0x2f;}
}
unless(defined(&PCIC_CIRRUS_EXT_CONTROL_1)) {
    sub PCIC_CIRRUS_EXT_CONTROL_1 () {	0x3;}
}
unless(defined(&PCIC_CIRRUS_EXT_CONTROL_1_PCI_INTR_MASK)) {
    sub PCIC_CIRRUS_EXT_CONTROL_1_PCI_INTR_MASK () {	0x18;}
}
unless(defined(&PCIC_IDENT_VADEM_MASK)) {
    sub PCIC_IDENT_VADEM_MASK () {	0x8;}
}
unless(defined(&PCIC_VG468_MISC)) {
    sub PCIC_VG468_MISC () {	0x3a;}
}
unless(defined(&PCIC_VG468_MISC_VADEMREV)) {
    sub PCIC_VG468_MISC_VADEMREV () {	0x40;}
}
unless(defined(&PCIC_VG469_VSELECT)) {
    sub PCIC_VG469_VSELECT () {	0x2f;}
}
unless(defined(&PCIC_VG469_VSELECT_VCC)) {
    sub PCIC_VG469_VSELECT_VCC () {	0x3;}
}
1;
