require '_h2ph_pre.ph';

no warnings 'redefine';

unless(defined(&_SDHCREG_H_)) {
    eval 'sub _SDHCREG_H_ () {1;}' unless defined(&_SDHCREG_H_);
    eval 'sub SDHC_PCI_BAR_START () { &PCI_MAPREG_START;}' unless defined(&SDHC_PCI_BAR_START);
    eval 'sub SDHC_PCI_BAR_END () { &PCI_MAPREG_END;}' unless defined(&SDHC_PCI_BAR_END);
    eval 'sub SDHC_PCI_INTERFACE_NO_DMA () {0x;}' unless defined(&SDHC_PCI_INTERFACE_NO_DMA);
    eval 'sub SDHC_PCI_INTERFACE_DMA () {0x1;}' unless defined(&SDHC_PCI_INTERFACE_DMA);
    eval 'sub SDHC_PCI_INTERFACE_VENDOR () {0x2;}' unless defined(&SDHC_PCI_INTERFACE_VENDOR);
    eval 'sub SDHC_DMA_ADDR () {0x;}' unless defined(&SDHC_DMA_ADDR);
    eval 'sub SDHC_BLOCK_SIZE () {0x4;}' unless defined(&SDHC_BLOCK_SIZE);
    eval 'sub SDHC_BLOCK_COUNT () {0x6;}' unless defined(&SDHC_BLOCK_COUNT);
    eval 'sub SDHC_BLOCK_COUNT_MAX () {512;}' unless defined(&SDHC_BLOCK_COUNT_MAX);
    eval 'sub SDHC_ARGUMENT () {0x8;}' unless defined(&SDHC_ARGUMENT);
    eval 'sub SDHC_TRANSFER_MODE () {0xc;}' unless defined(&SDHC_TRANSFER_MODE);
    eval 'sub SDHC_MULTI_BLOCK_MODE () {(1<<5);}' unless defined(&SDHC_MULTI_BLOCK_MODE);
    eval 'sub SDHC_READ_MODE () {(1<<4);}' unless defined(&SDHC_READ_MODE);
    eval 'sub SDHC_AUTO_CMD12_ENABLE () {(1<<2);}' unless defined(&SDHC_AUTO_CMD12_ENABLE);
    eval 'sub SDHC_BLOCK_COUNT_ENABLE () {(1<<1);}' unless defined(&SDHC_BLOCK_COUNT_ENABLE);
    eval 'sub SDHC_DMA_ENABLE () {(1<<0);}' unless defined(&SDHC_DMA_ENABLE);
    eval 'sub SDHC_COMMAND () {0xe;}' unless defined(&SDHC_COMMAND);
    eval 'sub SDHC_COMMAND_INDEX_SHIFT () {8;}' unless defined(&SDHC_COMMAND_INDEX_SHIFT);
    eval 'sub SDHC_COMMAND_INDEX_MASK () {0x3f;}' unless defined(&SDHC_COMMAND_INDEX_MASK);
    eval 'sub SDHC_COMMAND_TYPE_ABORT () {(3<<6);}' unless defined(&SDHC_COMMAND_TYPE_ABORT);
    eval 'sub SDHC_COMMAND_TYPE_RESUME () {(2<<6);}' unless defined(&SDHC_COMMAND_TYPE_RESUME);
    eval 'sub SDHC_COMMAND_TYPE_SUSPEND () {(1<<6);}' unless defined(&SDHC_COMMAND_TYPE_SUSPEND);
    eval 'sub SDHC_COMMAND_TYPE_NORMAL () {(0<<6);}' unless defined(&SDHC_COMMAND_TYPE_NORMAL);
    eval 'sub SDHC_DATA_PRESENT_SELECT () {(1<<5);}' unless defined(&SDHC_DATA_PRESENT_SELECT);
    eval 'sub SDHC_INDEX_CHECK_ENABLE () {(1<<4);}' unless defined(&SDHC_INDEX_CHECK_ENABLE);
    eval 'sub SDHC_CRC_CHECK_ENABLE () {(1<<3);}' unless defined(&SDHC_CRC_CHECK_ENABLE);
    eval 'sub SDHC_RESP_LEN_48_CHK_BUSY () {(3<<0);}' unless defined(&SDHC_RESP_LEN_48_CHK_BUSY);
    eval 'sub SDHC_RESP_LEN_48 () {(2<<0);}' unless defined(&SDHC_RESP_LEN_48);
    eval 'sub SDHC_RESP_LEN_136 () {(1<<0);}' unless defined(&SDHC_RESP_LEN_136);
    eval 'sub SDHC_NO_RESPONSE () {(0<<0);}' unless defined(&SDHC_NO_RESPONSE);
    eval 'sub SDHC_RESPONSE () {0x10;}' unless defined(&SDHC_RESPONSE);
    eval 'sub SDHC_DATA () {0x20;}' unless defined(&SDHC_DATA);
    eval 'sub SDHC_PRESENT_STATE () {0x24;}' unless defined(&SDHC_PRESENT_STATE);
    eval 'sub SDHC_CMD_LINE_SIGNAL_LEVEL () {(1<<24);}' unless defined(&SDHC_CMD_LINE_SIGNAL_LEVEL);
    eval 'sub SDHC_DAT3_LINE_LEVEL () {(1<<23);}' unless defined(&SDHC_DAT3_LINE_LEVEL);
    eval 'sub SDHC_DAT2_LINE_LEVEL () {(1<<22);}' unless defined(&SDHC_DAT2_LINE_LEVEL);
    eval 'sub SDHC_DAT1_LINE_LEVEL () {(1<<21);}' unless defined(&SDHC_DAT1_LINE_LEVEL);
    eval 'sub SDHC_DAT0_LINE_LEVEL () {(1<<20);}' unless defined(&SDHC_DAT0_LINE_LEVEL);
    eval 'sub SDHC_WRITE_PROTECT_SWITCH () {(1<<19);}' unless defined(&SDHC_WRITE_PROTECT_SWITCH);
    eval 'sub SDHC_CARD_DETECT_PIN_LEVEL () {(1<<18);}' unless defined(&SDHC_CARD_DETECT_PIN_LEVEL);
    eval 'sub SDHC_CARD_STATE_STABLE () {(1<<17);}' unless defined(&SDHC_CARD_STATE_STABLE);
    eval 'sub SDHC_CARD_INSERTED () {(1<<16);}' unless defined(&SDHC_CARD_INSERTED);
    eval 'sub SDHC_BUFFER_READ_ENABLE () {(1<<11);}' unless defined(&SDHC_BUFFER_READ_ENABLE);
    eval 'sub SDHC_BUFFER_WRITE_ENABLE () {(1<<10);}' unless defined(&SDHC_BUFFER_WRITE_ENABLE);
    eval 'sub SDHC_READ_TRANSFER_ACTIVE () {(1<<9);}' unless defined(&SDHC_READ_TRANSFER_ACTIVE);
    eval 'sub SDHC_WRITE_TRANSFER_ACTIVE () {(1<<8);}' unless defined(&SDHC_WRITE_TRANSFER_ACTIVE);
    eval 'sub SDHC_DAT_ACTIVE () {(1<<2);}' unless defined(&SDHC_DAT_ACTIVE);
    eval 'sub SDHC_CMD_INHIBIT_DAT () {(1<<1);}' unless defined(&SDHC_CMD_INHIBIT_DAT);
    eval 'sub SDHC_CMD_INHIBIT_CMD () {(1<<0);}' unless defined(&SDHC_CMD_INHIBIT_CMD);
    eval 'sub SDHC_CMD_INHIBIT_MASK () {0x3;}' unless defined(&SDHC_CMD_INHIBIT_MASK);
    eval 'sub SDHC_HOST_CTL () {0x28;}' unless defined(&SDHC_HOST_CTL);
    eval 'sub SDHC_HIGH_SPEED () {(1<<2);}' unless defined(&SDHC_HIGH_SPEED);
    eval 'sub SDHC_4BIT_MODE () {(1<<1);}' unless defined(&SDHC_4BIT_MODE);
    eval 'sub SDHC_LED_ON () {(1<<0);}' unless defined(&SDHC_LED_ON);
    eval 'sub SDHC_POWER_CTL () {0x29;}' unless defined(&SDHC_POWER_CTL);
    eval 'sub SDHC_VOLTAGE_SHIFT () {1;}' unless defined(&SDHC_VOLTAGE_SHIFT);
    eval 'sub SDHC_VOLTAGE_MASK () {0x7;}' unless defined(&SDHC_VOLTAGE_MASK);
    eval 'sub SDHC_VOLTAGE_3_3V () {0x7;}' unless defined(&SDHC_VOLTAGE_3_3V);
    eval 'sub SDHC_VOLTAGE_3_0V () {0x6;}' unless defined(&SDHC_VOLTAGE_3_0V);
    eval 'sub SDHC_VOLTAGE_1_8V () {0x5;}' unless defined(&SDHC_VOLTAGE_1_8V);
    eval 'sub SDHC_BUS_POWER () {(1<<0);}' unless defined(&SDHC_BUS_POWER);
    eval 'sub SDHC_BLOCK_GAP_CTL () {0x2a;}' unless defined(&SDHC_BLOCK_GAP_CTL);
    eval 'sub SDHC_WAKEUP_CTL () {0x2b;}' unless defined(&SDHC_WAKEUP_CTL);
    eval 'sub SDHC_CLOCK_CTL () {0x2c;}' unless defined(&SDHC_CLOCK_CTL);
    eval 'sub SDHC_SDCLK_DIV_SHIFT () {8;}' unless defined(&SDHC_SDCLK_DIV_SHIFT);
    eval 'sub SDHC_SDCLK_DIV_MASK () {0xff;}' unless defined(&SDHC_SDCLK_DIV_MASK);
    eval 'sub SDHC_SDCLK_ENABLE () {(1<<2);}' unless defined(&SDHC_SDCLK_ENABLE);
    eval 'sub SDHC_INTCLK_STABLE () {(1<<1);}' unless defined(&SDHC_INTCLK_STABLE);
    eval 'sub SDHC_INTCLK_ENABLE () {(1<<0);}' unless defined(&SDHC_INTCLK_ENABLE);
    eval 'sub SDHC_TIMEOUT_CTL () {0x2e;}' unless defined(&SDHC_TIMEOUT_CTL);
    eval 'sub SDHC_TIMEOUT_MAX () {0xe;}' unless defined(&SDHC_TIMEOUT_MAX);
    eval 'sub SDHC_SOFTWARE_RESET () {0x2f;}' unless defined(&SDHC_SOFTWARE_RESET);
    eval 'sub SDHC_RESET_MASK () {0x5;}' unless defined(&SDHC_RESET_MASK);
    eval 'sub SDHC_RESET_DAT () {(1<<2);}' unless defined(&SDHC_RESET_DAT);
    eval 'sub SDHC_RESET_CMD () {(1<<1);}' unless defined(&SDHC_RESET_CMD);
    eval 'sub SDHC_RESET_ALL () {(1<<0);}' unless defined(&SDHC_RESET_ALL);
    eval 'sub SDHC_NINTR_STATUS () {0x30;}' unless defined(&SDHC_NINTR_STATUS);
    eval 'sub SDHC_ERROR_INTERRUPT () {(1<<15);}' unless defined(&SDHC_ERROR_INTERRUPT);
    eval 'sub SDHC_CARD_INTERRUPT () {(1<<8);}' unless defined(&SDHC_CARD_INTERRUPT);
    eval 'sub SDHC_CARD_REMOVAL () {(1<<7);}' unless defined(&SDHC_CARD_REMOVAL);
    eval 'sub SDHC_CARD_INSERTION () {(1<<6);}' unless defined(&SDHC_CARD_INSERTION);
    eval 'sub SDHC_BUFFER_READ_READY () {(1<<5);}' unless defined(&SDHC_BUFFER_READ_READY);
    eval 'sub SDHC_BUFFER_WRITE_READY () {(1<<4);}' unless defined(&SDHC_BUFFER_WRITE_READY);
    eval 'sub SDHC_DMA_INTERRUPT () {(1<<3);}' unless defined(&SDHC_DMA_INTERRUPT);
    eval 'sub SDHC_BLOCK_GAP_EVENT () {(1<<2);}' unless defined(&SDHC_BLOCK_GAP_EVENT);
    eval 'sub SDHC_TRANSFER_COMPLETE () {(1<<1);}' unless defined(&SDHC_TRANSFER_COMPLETE);
    eval 'sub SDHC_COMMAND_COMPLETE () {(1<<0);}' unless defined(&SDHC_COMMAND_COMPLETE);
    eval 'sub SDHC_NINTR_STATUS_MASK () {0x81ff;}' unless defined(&SDHC_NINTR_STATUS_MASK);
    eval 'sub SDHC_EINTR_STATUS () {0x32;}' unless defined(&SDHC_EINTR_STATUS);
    eval 'sub SDHC_AUTO_CMD12_ERROR () {(1<<8);}' unless defined(&SDHC_AUTO_CMD12_ERROR);
    eval 'sub SDHC_CURRENT_LIMIT_ERROR () {(1<<7);}' unless defined(&SDHC_CURRENT_LIMIT_ERROR);
    eval 'sub SDHC_DATA_END_BIT_ERROR () {(1<<6);}' unless defined(&SDHC_DATA_END_BIT_ERROR);
    eval 'sub SDHC_DATA_CRC_ERROR () {(1<<5);}' unless defined(&SDHC_DATA_CRC_ERROR);
    eval 'sub SDHC_DATA_TIMEOUT_ERROR () {(1<<4);}' unless defined(&SDHC_DATA_TIMEOUT_ERROR);
    eval 'sub SDHC_CMD_INDEX_ERROR () {(1<<3);}' unless defined(&SDHC_CMD_INDEX_ERROR);
    eval 'sub SDHC_CMD_END_BIT_ERROR () {(1<<2);}' unless defined(&SDHC_CMD_END_BIT_ERROR);
    eval 'sub SDHC_CMD_CRC_ERROR () {(1<<1);}' unless defined(&SDHC_CMD_CRC_ERROR);
    eval 'sub SDHC_CMD_TIMEOUT_ERROR () {(1<<0);}' unless defined(&SDHC_CMD_TIMEOUT_ERROR);
    eval 'sub SDHC_EINTR_STATUS_MASK () {0x1ff;}' unless defined(&SDHC_EINTR_STATUS_MASK);
    eval 'sub SDHC_NINTR_STATUS_EN () {0x34;}' unless defined(&SDHC_NINTR_STATUS_EN);
    eval 'sub SDHC_EINTR_STATUS_EN () {0x36;}' unless defined(&SDHC_EINTR_STATUS_EN);
    eval 'sub SDHC_NINTR_SIGNAL_EN () {0x38;}' unless defined(&SDHC_NINTR_SIGNAL_EN);
    eval 'sub SDHC_NINTR_SIGNAL_MASK () {0x1ff;}' unless defined(&SDHC_NINTR_SIGNAL_MASK);
    eval 'sub SDHC_EINTR_SIGNAL_EN () {0x3a;}' unless defined(&SDHC_EINTR_SIGNAL_EN);
    eval 'sub SDHC_EINTR_SIGNAL_MASK () {0x1ff;}' unless defined(&SDHC_EINTR_SIGNAL_MASK);
    eval 'sub SDHC_CMD12_ERROR_STATUS () {0x3c;}' unless defined(&SDHC_CMD12_ERROR_STATUS);
    eval 'sub SDHC_CAPABILITIES () {0x40;}' unless defined(&SDHC_CAPABILITIES);
    eval 'sub SDHC_VOLTAGE_SUPP_1_8V () {(1<<26);}' unless defined(&SDHC_VOLTAGE_SUPP_1_8V);
    eval 'sub SDHC_VOLTAGE_SUPP_3_0V () {(1<<25);}' unless defined(&SDHC_VOLTAGE_SUPP_3_0V);
    eval 'sub SDHC_VOLTAGE_SUPP_3_3V () {(1<<24);}' unless defined(&SDHC_VOLTAGE_SUPP_3_3V);
    eval 'sub SDHC_DMA_SUPPORT () {(1<<22);}' unless defined(&SDHC_DMA_SUPPORT);
    eval 'sub SDHC_HIGH_SPEED_SUPP () {(1<<21);}' unless defined(&SDHC_HIGH_SPEED_SUPP);
    eval 'sub SDHC_MAX_BLK_LEN_512 () {0;}' unless defined(&SDHC_MAX_BLK_LEN_512);
    eval 'sub SDHC_MAX_BLK_LEN_1024 () {1;}' unless defined(&SDHC_MAX_BLK_LEN_1024);
    eval 'sub SDHC_MAX_BLK_LEN_2048 () {2;}' unless defined(&SDHC_MAX_BLK_LEN_2048);
    eval 'sub SDHC_MAX_BLK_LEN_SHIFT () {16;}' unless defined(&SDHC_MAX_BLK_LEN_SHIFT);
    eval 'sub SDHC_MAX_BLK_LEN_MASK () {0x3;}' unless defined(&SDHC_MAX_BLK_LEN_MASK);
    eval 'sub SDHC_BASE_FREQ_SHIFT () {8;}' unless defined(&SDHC_BASE_FREQ_SHIFT);
    eval 'sub SDHC_BASE_FREQ_MASK () {0x3f;}' unless defined(&SDHC_BASE_FREQ_MASK);
    eval 'sub SDHC_TIMEOUT_FREQ_UNIT () {(1<<7);}' unless defined(&SDHC_TIMEOUT_FREQ_UNIT);
    eval 'sub SDHC_TIMEOUT_FREQ_SHIFT () {0;}' unless defined(&SDHC_TIMEOUT_FREQ_SHIFT);
    eval 'sub SDHC_TIMEOUT_FREQ_MASK () {0x1f;}' unless defined(&SDHC_TIMEOUT_FREQ_MASK);
    eval 'sub SDHC_MAX_CAPABILITIES () {0x48;}' unless defined(&SDHC_MAX_CAPABILITIES);
    eval 'sub SDHC_SLOT_INTR_STATUS () {0xfc;}' unless defined(&SDHC_SLOT_INTR_STATUS);
    eval 'sub SDHC_HOST_CTL_VERSION () {0xfe;}' unless defined(&SDHC_HOST_CTL_VERSION);
    eval 'sub SDHC_SPEC_VERS_SHIFT () {0;}' unless defined(&SDHC_SPEC_VERS_SHIFT);
    eval 'sub SDHC_SPEC_VERS_MASK () {0xff;}' unless defined(&SDHC_SPEC_VERS_MASK);
    eval 'sub SDHC_VENDOR_VERS_SHIFT () {8;}' unless defined(&SDHC_VENDOR_VERS_SHIFT);
    eval 'sub SDHC_VENDOR_VERS_MASK () {0xff;}' unless defined(&SDHC_VENDOR_VERS_MASK);
    eval 'sub SDHC_BASE_FREQ_KHZ {
        my($cap) = @_;
	    eval q((((($cap) >>  &SDHC_BASE_FREQ_SHIFT) &  &SDHC_BASE_FREQ_MASK) * 1000));
    }' unless defined(&SDHC_BASE_FREQ_KHZ);
    eval 'sub SDHC_TIMEOUT_FREQ {
        my($cap) = @_;
	    eval q(((($cap) >>  &SDHC_TIMEOUT_FREQ_SHIFT) &  &SDHC_TIMEOUT_FREQ_MASK));
    }' unless defined(&SDHC_TIMEOUT_FREQ);
    eval 'sub SDHC_TIMEOUT_FREQ_KHZ {
        my($cap) = @_;
	    eval q(((($cap) &  &SDHC_TIMEOUT_FREQ_UNIT) ?  &SDHC_TIMEOUT_FREQ($cap) * 1000:  &SDHC_TIMEOUT_FREQ($cap)));
    }' unless defined(&SDHC_TIMEOUT_FREQ_KHZ);
    eval 'sub SDHC_SPEC_VERSION {
        my($hcv) = @_;
	    eval q(((($hcv) >>  &SDHC_SPEC_VERS_SHIFT) &  &SDHC_SPEC_VERS_MASK));
    }' unless defined(&SDHC_SPEC_VERSION);
    eval 'sub SDHC_VENDOR_VERSION {
        my($hcv) = @_;
	    eval q(((($hcv) >>  &SDHC_VENDOR_VERS_SHIFT) &  &SDHC_VENDOR_VERS_MASK));
    }' unless defined(&SDHC_VENDOR_VERSION);
    eval 'sub SDHC_PRESENT_STATE_BITS () {"\\20\\31CL\\30D3L\\27D2L\\26D1L\\25D0L\\24WPS\\23CD\\22CSS\\21CI" "\\14BRE\\13BWE\\12RTA\\11WTA\\3DLA\\2CID\\1CIC";}' unless defined(&SDHC_PRESENT_STATE_BITS);
    eval 'sub SDHC_NINTR_STATUS_BITS () {"\\20\\20ERROR\\11CARD\\10REMOVAL\\7INSERTION\\6READ\\5WRITE" "\\4DMA\\3GAP\\2XFER\\1CMD";}' unless defined(&SDHC_NINTR_STATUS_BITS);
    eval 'sub SDHC_EINTR_STATUS_BITS () {"\\20\\11ACMD12\\10CL\\7DEB\\6DCRC\\5DT\\4CI\\3CEB\\2CCRC\\1CT";}' unless defined(&SDHC_EINTR_STATUS_BITS);
    eval 'sub SDHC_CAPABILITIES_BITS () {"\\20\\33Vdd1.8V\\32Vdd3.0V\\31Vdd3.3V\\30SUSPEND\\27DMA\\26HIGHSPEED";}' unless defined(&SDHC_CAPABILITIES_BITS);
}
1;
