require '_h2ph_pre.ph';

no warnings 'redefine';

unless(defined(&_DEV_PCI_PCCBBREG_H_)) {
    eval 'sub _DEV_PCI_PCCBBREG_H_ () {1;}' unless defined(&_DEV_PCI_PCCBBREG_H_);
    eval 'sub PCI_SOCKBASE () {0x10;}' unless defined(&PCI_SOCKBASE);
    eval 'sub PCI_BUSNUM () {0x18;}' unless defined(&PCI_BUSNUM);
    eval 'sub PCI_BCR_INTR () {0x3c;}' unless defined(&PCI_BCR_INTR);
    eval 'sub PCI_LEGACY () {0x44;}' unless defined(&PCI_LEGACY);
    eval 'sub PCI_SYSCTRL () {0x80;}' unless defined(&PCI_SYSCTRL);
    eval 'sub PCI_CBCTRL () {0x90;}' unless defined(&PCI_CBCTRL);
    eval 'sub PCI_CLASS_INTERFACE_MASK () {0xffffff00;}' unless defined(&PCI_CLASS_INTERFACE_MASK);
    eval 'sub PCI_CLASS_INTERFACE_YENTA () {0x6070000;}' unless defined(&PCI_CLASS_INTERFACE_YENTA);
    eval 'sub PCI_CB_LSCP_REG () {0x18;}' unless defined(&PCI_CB_LSCP_REG);
    eval 'sub PCI_CB_MEMBASE0 () {0x1c;}' unless defined(&PCI_CB_MEMBASE0);
    eval 'sub PCI_CB_MEMLIMIT0 () {0x20;}' unless defined(&PCI_CB_MEMLIMIT0);
    eval 'sub PCI_CB_MEMBASE1 () {0x24;}' unless defined(&PCI_CB_MEMBASE1);
    eval 'sub PCI_CB_MEMLIMIT1 () {0x28;}' unless defined(&PCI_CB_MEMLIMIT1);
    eval 'sub PCI_CB_IOBASE0 () {0x2c;}' unless defined(&PCI_CB_IOBASE0);
    eval 'sub PCI_CB_IOLIMIT0 () {0x30;}' unless defined(&PCI_CB_IOLIMIT0);
    eval 'sub PCI_CB_IOBASE1 () {0x34;}' unless defined(&PCI_CB_IOBASE1);
    eval 'sub PCI_CB_IOLIMIT1 () {0x38;}' unless defined(&PCI_CB_IOLIMIT1);
    eval 'sub PCI_CB_LATENCY_SHIFT () {24;}' unless defined(&PCI_CB_LATENCY_SHIFT);
    eval 'sub PCI_CB_LATENCY_MASK () {0xff;}' unless defined(&PCI_CB_LATENCY_MASK);
    eval 'sub PCI_CB_LATENCY {
        my($x) = @_;
	    eval q(( (($x) >>  &PCI_CB_LATENCY_SHIFT) &  &PCI_CB_LATENCY_MASK));
    }' unless defined(&PCI_CB_LATENCY);
    eval 'sub CB_SOCKET_EVENT () {0x;}' unless defined(&CB_SOCKET_EVENT);
    eval 'sub CB_SOCKET_EVENT_CSTS () {0x1;}' unless defined(&CB_SOCKET_EVENT_CSTS);
    eval 'sub CB_SOCKET_EVENT_CD () {0x6;}' unless defined(&CB_SOCKET_EVENT_CD);
    eval 'sub CB_SOCKET_EVENT_CD1 () {0x2;}' unless defined(&CB_SOCKET_EVENT_CD1);
    eval 'sub CB_SOCKET_EVENT_CD2 () {0x4;}' unless defined(&CB_SOCKET_EVENT_CD2);
    eval 'sub CB_SOCKET_EVENT_POWER () {0x8;}' unless defined(&CB_SOCKET_EVENT_POWER);
    eval 'sub CB_SOCKET_MASK () {0x4;}' unless defined(&CB_SOCKET_MASK);
    eval 'sub CB_SOCKET_MASK_CSTS () {0x1;}' unless defined(&CB_SOCKET_MASK_CSTS);
    eval 'sub CB_SOCKET_MASK_CD () {0x6;}' unless defined(&CB_SOCKET_MASK_CD);
    eval 'sub CB_SOCKET_MASK_POWER () {0x8;}' unless defined(&CB_SOCKET_MASK_POWER);
    eval 'sub CB_SOCKET_STAT () {0x8;}' unless defined(&CB_SOCKET_STAT);
    eval 'sub CB_SOCKET_STAT_CARDSTS () {0x1;}' unless defined(&CB_SOCKET_STAT_CARDSTS);
    eval 'sub CB_SOCKET_STAT_CD1 () {0x2;}' unless defined(&CB_SOCKET_STAT_CD1);
    eval 'sub CB_SOCKET_STAT_CD2 () {0x4;}' unless defined(&CB_SOCKET_STAT_CD2);
    eval 'sub CB_SOCKET_STAT_CD () {0x6;}' unless defined(&CB_SOCKET_STAT_CD);
    eval 'sub CB_SOCKET_STAT_PWRCYCLE () {0x8;}' unless defined(&CB_SOCKET_STAT_PWRCYCLE);
    eval 'sub CB_SOCKET_STAT_16BIT () {0x10;}' unless defined(&CB_SOCKET_STAT_16BIT);
    eval 'sub CB_SOCKET_STAT_CB () {0x20;}' unless defined(&CB_SOCKET_STAT_CB);
    eval 'sub CB_SOCKET_STAT_IREQ () {0x40;}' unless defined(&CB_SOCKET_STAT_IREQ);
    eval 'sub CB_SOCKET_STAT_NOTCARD () {0x80;}' unless defined(&CB_SOCKET_STAT_NOTCARD);
    eval 'sub CB_SOCKET_STAT_DATALOST () {0x100;}' unless defined(&CB_SOCKET_STAT_DATALOST);
    eval 'sub CB_SOCKET_STAT_BADVCC () {0x200;}' unless defined(&CB_SOCKET_STAT_BADVCC);
    eval 'sub CB_SOCKET_STAT_5VCARD () {0x400;}' unless defined(&CB_SOCKET_STAT_5VCARD);
    eval 'sub CB_SOCKET_STAT_3VCARD () {0x800;}' unless defined(&CB_SOCKET_STAT_3VCARD);
    eval 'sub CB_SOCKET_STAT_XVCARD () {0x1000;}' unless defined(&CB_SOCKET_STAT_XVCARD);
    eval 'sub CB_SOCKET_STAT_YVCARD () {0x2000;}' unless defined(&CB_SOCKET_STAT_YVCARD);
    eval 'sub CB_SOCKET_STAT_5VSOCK () {0x10000000;}' unless defined(&CB_SOCKET_STAT_5VSOCK);
    eval 'sub CB_SOCKET_STAT_3VSOCK () {0x20000000;}' unless defined(&CB_SOCKET_STAT_3VSOCK);
    eval 'sub CB_SOCKET_STAT_XVSOCK () {0x40000000;}' unless defined(&CB_SOCKET_STAT_XVSOCK);
    eval 'sub CB_SOCKET_STAT_YVSOCK () {0x80000000;}' unless defined(&CB_SOCKET_STAT_YVSOCK);
    eval 'sub CB_SOCKET_FORCE () {0xc;}' unless defined(&CB_SOCKET_FORCE);
    eval 'sub CB_SOCKET_FORCE_BADVCC () {0x200;}' unless defined(&CB_SOCKET_FORCE_BADVCC);
    eval 'sub CB_SOCKET_CTRL () {0x10;}' unless defined(&CB_SOCKET_CTRL);
    eval 'sub CB_SOCKET_CTRL_VPPMASK () {0x7;}' unless defined(&CB_SOCKET_CTRL_VPPMASK);
    eval 'sub CB_SOCKET_CTRL_VPP_OFF () {0x;}' unless defined(&CB_SOCKET_CTRL_VPP_OFF);
    eval 'sub CB_SOCKET_CTRL_VPP_12V () {0x1;}' unless defined(&CB_SOCKET_CTRL_VPP_12V);
    eval 'sub CB_SOCKET_CTRL_VPP_5V () {0x2;}' unless defined(&CB_SOCKET_CTRL_VPP_5V);
    eval 'sub CB_SOCKET_CTRL_VPP_3V () {0x3;}' unless defined(&CB_SOCKET_CTRL_VPP_3V);
    eval 'sub CB_SOCKET_CTRL_VPP_XV () {0x4;}' unless defined(&CB_SOCKET_CTRL_VPP_XV);
    eval 'sub CB_SOCKET_CTRL_VPP_YV () {0x5;}' unless defined(&CB_SOCKET_CTRL_VPP_YV);
    eval 'sub CB_SOCKET_CTRL_VCCMASK () {0x70;}' unless defined(&CB_SOCKET_CTRL_VCCMASK);
    eval 'sub CB_SOCKET_CTRL_VCC_OFF () {0x;}' unless defined(&CB_SOCKET_CTRL_VCC_OFF);
    eval 'sub CB_SOCKET_CTRL_VCC_5V () {0x20;}' unless defined(&CB_SOCKET_CTRL_VCC_5V);
    eval 'sub CB_SOCKET_CTRL_VCC_3V () {0x30;}' unless defined(&CB_SOCKET_CTRL_VCC_3V);
    eval 'sub CB_SOCKET_CTRL_VCC_XV () {0x40;}' unless defined(&CB_SOCKET_CTRL_VCC_XV);
    eval 'sub CB_SOCKET_CTRL_VCC_YV () {0x50;}' unless defined(&CB_SOCKET_CTRL_VCC_YV);
    eval 'sub CB_SOCKET_CTRL_STOPCLK () {0x80;}' unless defined(&CB_SOCKET_CTRL_STOPCLK);
    eval 'sub PCCBB_SOCKEVENT_BITS () {"\\020\\001CSTS\\002CD1\\003CD2\\004PWR";}' unless defined(&PCCBB_SOCKEVENT_BITS);
    eval 'sub PCCBB_SOCKSTATE_BITS () {"\\020\\001CSTS\\002CD1\\003CD3\\004PWR\\00516BIT\\006CB\\007CINT\\010NOTA" "\\011DLOST\\012BADVCC\\0135v\\0143v\\015Xv\\016Yv\\0355vS\\0363vS\\037XvS\\040YvS";}' unless defined(&PCCBB_SOCKSTATE_BITS);
    eval 'sub CB_BCR_RESET_ENABLE () {0x400000;}' unless defined(&CB_BCR_RESET_ENABLE);
    eval 'sub CB_BCR_INTR_IREQ_ENABLE () {0x800000;}' unless defined(&CB_BCR_INTR_IREQ_ENABLE);
    eval 'sub CB_BCR_PREFETCH_MEMWIN0 () {0x1000000;}' unless defined(&CB_BCR_PREFETCH_MEMWIN0);
    eval 'sub CB_BCR_PREFETCH_MEMWIN1 () {0x2000000;}' unless defined(&CB_BCR_PREFETCH_MEMWIN1);
    eval 'sub CB_BCR_WRITE_POST_ENABLE () {0x4000000;}' unless defined(&CB_BCR_WRITE_POST_ENABLE);
    eval 'sub PCI12XX_MMCTRL () {0x84;}' unless defined(&PCI12XX_MMCTRL);
    eval 'sub PCI12XX_MFUNC () {0x8c;}' unless defined(&PCI12XX_MFUNC);
    eval 'sub PCI12XX_MFUNC_PIN0 () {0xf;}' unless defined(&PCI12XX_MFUNC_PIN0);
    eval 'sub PCI12XX_MFUNC_PIN0_INTA () {0x2;}' unless defined(&PCI12XX_MFUNC_PIN0_INTA);
    eval 'sub PCI12XX_MFUNC_PIN1 () {0xf0;}' unless defined(&PCI12XX_MFUNC_PIN1);
    eval 'sub PCI12XX_MFUNC_PIN1_INTB () {0x20;}' unless defined(&PCI12XX_MFUNC_PIN1_INTB);
    eval 'sub PCI12XX_MFUNC_PIN2 () {0xf00;}' unless defined(&PCI12XX_MFUNC_PIN2);
    eval 'sub PCI12XX_MFUNC_PIN3 () {0xf000;}' unless defined(&PCI12XX_MFUNC_PIN3);
    eval 'sub PCI12XX_MFUNC_PIN4 () {0xf0000;}' unless defined(&PCI12XX_MFUNC_PIN4);
    eval 'sub PCI12XX_MFUNC_PIN5 () {0xf00000;}' unless defined(&PCI12XX_MFUNC_PIN5);
    eval 'sub PCI12XX_MFUNC_PIN6 () {0xf000000;}' unless defined(&PCI12XX_MFUNC_PIN6);
    eval 'sub PCI113X_CBCTRL_INT_SERIAL () {0x40000;}' unless defined(&PCI113X_CBCTRL_INT_SERIAL);
    eval 'sub PCI113X_CBCTRL_INT_ISA () {0x20000;}' unless defined(&PCI113X_CBCTRL_INT_ISA);
    eval 'sub PCI113X_CBCTRL_INT_MASK () {0x60000;}' unless defined(&PCI113X_CBCTRL_INT_MASK);
    eval 'sub PCI113X_CBCTRL_RIENB () {0x8000;}' unless defined(&PCI113X_CBCTRL_RIENB);
    eval 'sub PCI113X_CBCTRL_ZVENAB () {0x4000;}' unless defined(&PCI113X_CBCTRL_ZVENAB);
    eval 'sub PCI113X_CBCTRL_PCI_IRQ_ENA () {0x2000;}' unless defined(&PCI113X_CBCTRL_PCI_IRQ_ENA);
    eval 'sub PCI113X_CBCTRL_PCI_INTR () {0x1000;}' unless defined(&PCI113X_CBCTRL_PCI_INTR);
    eval 'sub PCI113X_CBCTRL_PCI_CSC () {0x800;}' unless defined(&PCI113X_CBCTRL_PCI_CSC);
    eval 'sub PCI113X_CBCTRL_PCI_CSC_D () {0x400;}' unless defined(&PCI113X_CBCTRL_PCI_CSC_D);
    eval 'sub PCI113X_CBCTRL_SPK_ENA () {0x200;}' unless defined(&PCI113X_CBCTRL_SPK_ENA);
    eval 'sub PCI113X_CBCTRL_INTR_DET () {0x100;}' unless defined(&PCI113X_CBCTRL_INTR_DET);
    eval 'sub PCI12XX_SYSCTRL_INTRTIE () {0x20000000;}' unless defined(&PCI12XX_SYSCTRL_INTRTIE);
    eval 'sub PCI12XX_SYSCTRL_VCCPROT () {0x200000;}' unless defined(&PCI12XX_SYSCTRL_VCCPROT);
    eval 'sub PCI12XX_SYSCTRL_PWRSAVE () {0x40;}' unless defined(&PCI12XX_SYSCTRL_PWRSAVE);
    eval 'sub PCI12XX_SYSCTRL_SUBSYSRW () {0x20;}' unless defined(&PCI12XX_SYSCTRL_SUBSYSRW);
    eval 'sub PCI12XX_SYSCTRL_CB_DPAR () {0x10;}' unless defined(&PCI12XX_SYSCTRL_CB_DPAR);
    eval 'sub PCI12XX_SYSCTRL_CDMA_EN () {0x8;}' unless defined(&PCI12XX_SYSCTRL_CDMA_EN);
    eval 'sub PCI12XX_SYSCTRL_KEEPCLK () {0x2;}' unless defined(&PCI12XX_SYSCTRL_KEEPCLK);
    eval 'sub PCI12XX_SYSCTRL_RIMUX () {0x1;}' unless defined(&PCI12XX_SYSCTRL_RIMUX);
    eval 'sub PCI12XX_CBCTRL_CSC () {0x20000000;}' unless defined(&PCI12XX_CBCTRL_CSC);
    eval 'sub PCI12XX_CBCTRL_ASYNC_CSC () {0x1000000;}' unless defined(&PCI12XX_CBCTRL_ASYNC_CSC);
    eval 'sub PCI12XX_CBCTRL_INT_SERIAL () {0x60000;}' unless defined(&PCI12XX_CBCTRL_INT_SERIAL);
    eval 'sub PCI12XX_CBCTRL_INT_PCI_SERIAL () {0x40000;}' unless defined(&PCI12XX_CBCTRL_INT_PCI_SERIAL);
    eval 'sub PCI12XX_CBCTRL_INT_ISA () {0x20000;}' unless defined(&PCI12XX_CBCTRL_INT_ISA);
    eval 'sub PCI12XX_CBCTRL_INT_PCI () {0x;}' unless defined(&PCI12XX_CBCTRL_INT_PCI);
    eval 'sub PCI12XX_CBCTRL_INT_MASK () {0x60000;}' unless defined(&PCI12XX_CBCTRL_INT_MASK);
    eval 'sub PCI12XX_CBCTRL_RIENB () {0x8000;}' unless defined(&PCI12XX_CBCTRL_RIENB);
    eval 'sub PCI12XX_CBCTRL_ZVENAB () {0x4000;}' unless defined(&PCI12XX_CBCTRL_ZVENAB);
    eval 'sub PCI12XX_CBCTRL_AUD2MUX () {0x400;}' unless defined(&PCI12XX_CBCTRL_AUD2MUX);
    eval 'sub PCI12XX_CBCTRL_SPK_ENA () {0x200;}' unless defined(&PCI12XX_CBCTRL_SPK_ENA);
    eval 'sub PCI12XX_CBCTRL_INTR_DET () {0x100;}' unless defined(&PCI12XX_CBCTRL_INTR_DET);
    eval 'sub CB_BCRI_RL_3E0_ENA () {0x8000000;}' unless defined(&CB_BCRI_RL_3E0_ENA);
    eval 'sub CB_BCRI_RL_3E2_ENA () {0x10000000;}' unless defined(&CB_BCRI_RL_3E2_ENA);
    eval 'sub TOPIC_SOCKET_CTRL () {0x90;}' unless defined(&TOPIC_SOCKET_CTRL);
    eval 'sub TOPIC_SOCKET_CTRL_SCR_IRQSEL () {0x1;}' unless defined(&TOPIC_SOCKET_CTRL_SCR_IRQSEL);
    eval 'sub TOPIC_SLOT_CTRL () {0xa0;}' unless defined(&TOPIC_SLOT_CTRL);
    eval 'sub TOPIC_SLOT_CTRL_SLOTON () {0x80;}' unless defined(&TOPIC_SLOT_CTRL_SLOTON);
    eval 'sub TOPIC_SLOT_CTRL_SLOTEN () {0x40;}' unless defined(&TOPIC_SLOT_CTRL_SLOTEN);
    eval 'sub TOPIC_SLOT_CTRL_ID_LOCK () {0x20;}' unless defined(&TOPIC_SLOT_CTRL_ID_LOCK);
    eval 'sub TOPIC_SLOT_CTRL_ID_WP () {0x10;}' unless defined(&TOPIC_SLOT_CTRL_ID_WP);
    eval 'sub TOPIC_SLOT_CTRL_PORT_MASK () {0xc;}' unless defined(&TOPIC_SLOT_CTRL_PORT_MASK);
    eval 'sub TOPIC_SLOT_CTRL_PORT_SHIFT () {2;}' unless defined(&TOPIC_SLOT_CTRL_PORT_SHIFT);
    eval 'sub TOPIC_SLOT_CTRL_OSF_MASK () {0x3;}' unless defined(&TOPIC_SLOT_CTRL_OSF_MASK);
    eval 'sub TOPIC_SLOT_CTRL_OSF_SHIFT () {0;}' unless defined(&TOPIC_SLOT_CTRL_OSF_SHIFT);
    eval 'sub TOPIC_SLOT_CTRL_INTB () {0x2000;}' unless defined(&TOPIC_SLOT_CTRL_INTB);
    eval 'sub TOPIC_SLOT_CTRL_INTA () {0x1000;}' unless defined(&TOPIC_SLOT_CTRL_INTA);
    eval 'sub TOPIC_SLOT_CTRL_INT_MASK () {0x3000;}' unless defined(&TOPIC_SLOT_CTRL_INT_MASK);
    eval 'sub TOPIC_SLOT_CTRL_CLOCK_MASK () {0xc00;}' unless defined(&TOPIC_SLOT_CTRL_CLOCK_MASK);
    eval 'sub TOPIC_SLOT_CTRL_CLOCK_2 () {0x800;}' unless defined(&TOPIC_SLOT_CTRL_CLOCK_2);
    eval 'sub TOPIC_SLOT_CTRL_CLOCK_1 () {0x400;}' unless defined(&TOPIC_SLOT_CTRL_CLOCK_1);
    eval 'sub TOPIC_SLOT_CTRL_CLOCK_0 () {0x;}' unless defined(&TOPIC_SLOT_CTRL_CLOCK_0);
    eval 'sub TOPIC97_SLOT_CTRL_STSIRQP () {0x400;}' unless defined(&TOPIC97_SLOT_CTRL_STSIRQP);
    eval 'sub TOPIC97_SLOT_CTRL_IRQP () {0x200;}' unless defined(&TOPIC97_SLOT_CTRL_IRQP);
    eval 'sub TOPIC97_SLOT_CTRL_PCIINT () {0x100;}' unless defined(&TOPIC97_SLOT_CTRL_PCIINT);
    eval 'sub TOPIC_SLOT_CTRL_CARDBUS () {0x80000000;}' unless defined(&TOPIC_SLOT_CTRL_CARDBUS);
    eval 'sub TOPIC_SLOT_CTRL_VS1 () {0x4000000;}' unless defined(&TOPIC_SLOT_CTRL_VS1);
    eval 'sub TOPIC_SLOT_CTRL_VS2 () {0x2000000;}' unless defined(&TOPIC_SLOT_CTRL_VS2);
    eval 'sub TOPIC_SLOT_CTRL_SWDETECT () {0x1000000;}' unless defined(&TOPIC_SLOT_CTRL_SWDETECT);
    eval 'sub TOPIC_REG_CTRL () {0xa4;}' unless defined(&TOPIC_REG_CTRL);
    eval 'sub TOPIC_REG_CTRL_RESUME_RESET () {0x80000000;}' unless defined(&TOPIC_REG_CTRL_RESUME_RESET);
    eval 'sub TOPIC_REG_CTRL_REMOVE_RESET () {0x40000000;}' unless defined(&TOPIC_REG_CTRL_REMOVE_RESET);
    eval 'sub TOPIC97_REG_CTRL_CLKRUN_ENA () {0x20000000;}' unless defined(&TOPIC97_REG_CTRL_CLKRUN_ENA);
    eval 'sub TOPIC97_REG_CTRL_TESTMODE () {0x10000000;}' unless defined(&TOPIC97_REG_CTRL_TESTMODE);
    eval 'sub TOPIC97_REG_CTRL_IOPLUP () {0x8000000;}' unless defined(&TOPIC97_REG_CTRL_IOPLUP);
    eval 'sub TOPIC_REG_CTRL_BUFOFF_PWROFF () {0x2000000;}' unless defined(&TOPIC_REG_CTRL_BUFOFF_PWROFF);
    eval 'sub TOPIC_REG_CTRL_BUFOFF_SIGOFF () {0x1000000;}' unless defined(&TOPIC_REG_CTRL_BUFOFF_SIGOFF);
    eval 'sub TOPIC97_REG_CTRL_CB_DEV_MASK () {0xf800;}' unless defined(&TOPIC97_REG_CTRL_CB_DEV_MASK);
    eval 'sub TOPIC97_REG_CTRL_CB_DEV_SHIFT () {11;}' unless defined(&TOPIC97_REG_CTRL_CB_DEV_SHIFT);
    eval 'sub TOPIC97_REG_CTRL_RI_DISABLE () {0x4;}' unless defined(&TOPIC97_REG_CTRL_RI_DISABLE);
    eval 'sub TOPIC97_REG_CTRL_CAUDIO_OFF () {0x2;}' unless defined(&TOPIC97_REG_CTRL_CAUDIO_OFF);
    eval 'sub TOPIC_REG_CTRL_CAUDIO_INVERT () {0x1;}' unless defined(&TOPIC_REG_CTRL_CAUDIO_INVERT);
    eval 'sub TOPIC100_PMCSR () {0x84;}' unless defined(&TOPIC100_PMCSR);
    eval 'sub TOPIC100_PMCSR_MASK () {0x3;}' unless defined(&TOPIC100_PMCSR_MASK);
    eval 'sub TOPIC100_PMCSR_D0 () {0x;}' unless defined(&TOPIC100_PMCSR_D0);
    eval 'sub O2MICRO_RESERVED1 () {0x94;}' unless defined(&O2MICRO_RESERVED1);
    eval 'sub O2MICRO_RESERVED2 () {0xd4;}' unless defined(&O2MICRO_RESERVED2);
    eval 'sub O2MICRO_RES_READ_PREFETCH () {0x2;}' unless defined(&O2MICRO_RES_READ_PREFETCH);
    eval 'sub O2MICRO_RES_WRITE_BURST () {0x8;}' unless defined(&O2MICRO_RES_WRITE_BURST);
}
1;
