require '_h2ph_pre.ph';

no warnings 'redefine';

unless(defined(&IOASIC_SLOT_0_START)) {
    sub IOASIC_SLOT_0_START () {	0x;}
}
unless(defined(&IOASIC_SLOT_1_START)) {
    sub IOASIC_SLOT_1_START () {	0x40000;}
}
unless(defined(&IOASIC_SLOT_2_START)) {
    sub IOASIC_SLOT_2_START () {	0x80000;}
}
unless(defined(&IOASIC_SLOT_3_START)) {
    sub IOASIC_SLOT_3_START () {	0xc0000;}
}
unless(defined(&IOASIC_SLOT_4_START)) {
    sub IOASIC_SLOT_4_START () {	0x100000;}
}
unless(defined(&IOASIC_SLOT_5_START)) {
    sub IOASIC_SLOT_5_START () {	0x140000;}
}
unless(defined(&IOASIC_SLOT_6_START)) {
    sub IOASIC_SLOT_6_START () {	0x180000;}
}
unless(defined(&IOASIC_SLOT_7_START)) {
    sub IOASIC_SLOT_7_START () {	0x1c0000;}
}
unless(defined(&IOASIC_SLOT_8_START)) {
    sub IOASIC_SLOT_8_START () {	0x200000;}
}
unless(defined(&IOASIC_SLOT_9_START)) {
    sub IOASIC_SLOT_9_START () {	0x240000;}
}
unless(defined(&IOASIC_SLOT_10_START)) {
    sub IOASIC_SLOT_10_START () {	0x280000;}
}
unless(defined(&IOASIC_SLOT_11_START)) {
    sub IOASIC_SLOT_11_START () {	0x2c0000;}
}
unless(defined(&IOASIC_SLOT_12_START)) {
    sub IOASIC_SLOT_12_START () {	0x300000;}
}
unless(defined(&IOASIC_SLOT_13_START)) {
    sub IOASIC_SLOT_13_START () {	0x340000;}
}
unless(defined(&IOASIC_SLOT_14_START)) {
    sub IOASIC_SLOT_14_START () {	0x380000;}
}
unless(defined(&IOASIC_SLOT_15_START)) {
    sub IOASIC_SLOT_15_START () {	0x3c0000;}
}
unless(defined(&IOASIC_SLOTS_END)) {
    sub IOASIC_SLOTS_END () {	0x3fffff;}
}
unless(defined(&IOASIC_SCSI_DMAPTR)) {
    sub IOASIC_SCSI_DMAPTR () {	 &IOASIC_SLOT_1_START+0x;}
}
unless(defined(&IOASIC_SCSI_NEXTPTR)) {
    sub IOASIC_SCSI_NEXTPTR () {	 &IOASIC_SLOT_1_START+0x10;}
}
unless(defined(&IOASIC_LANCE_DMAPTR)) {
    sub IOASIC_LANCE_DMAPTR () {	 &IOASIC_SLOT_1_START+0x20;}
}
unless(defined(&IOASIC_SCC_T1_DMAPTR)) {
    sub IOASIC_SCC_T1_DMAPTR () {	 &IOASIC_SLOT_1_START+0x30;}
}
unless(defined(&IOASIC_SCC_R1_DMAPTR)) {
    sub IOASIC_SCC_R1_DMAPTR () {	 &IOASIC_SLOT_1_START+0x40;}
}
unless(defined(&IOASIC_SCC_T2_DMAPTR)) {
    sub IOASIC_SCC_T2_DMAPTR () {	 &IOASIC_SLOT_1_START+0x50;}
}
unless(defined(&IOASIC_SCC_R2_DMAPTR)) {
    sub IOASIC_SCC_R2_DMAPTR () {	 &IOASIC_SLOT_1_START+0x60;}
}
unless(defined(&IOASIC_FLOPPY_DMAPTR)) {
    sub IOASIC_FLOPPY_DMAPTR () {	 &IOASIC_SLOT_1_START+0x70;}
}
unless(defined(&IOASIC_ISDN_X_DMAPTR)) {
    sub IOASIC_ISDN_X_DMAPTR () {	 &IOASIC_SLOT_1_START+0x80;}
}
unless(defined(&IOASIC_ISDN_X_NEXTPTR)) {
    sub IOASIC_ISDN_X_NEXTPTR () {	 &IOASIC_SLOT_1_START+0x90;}
}
unless(defined(&IOASIC_ISDN_R_DMAPTR)) {
    sub IOASIC_ISDN_R_DMAPTR () {	 &IOASIC_SLOT_1_START+0xa0;}
}
unless(defined(&IOASIC_ISDN_R_NEXTPTR)) {
    sub IOASIC_ISDN_R_NEXTPTR () {	 &IOASIC_SLOT_1_START+0xb0;}
}
unless(defined(&IOASIC_BUFF0)) {
    sub IOASIC_BUFF0 () {	 &IOASIC_SLOT_1_START+0xc0;}
}
unless(defined(&IOASIC_BUFF1)) {
    sub IOASIC_BUFF1 () {	 &IOASIC_SLOT_1_START+0xd0;}
}
unless(defined(&IOASIC_BUFF2)) {
    sub IOASIC_BUFF2 () {	 &IOASIC_SLOT_1_START+0xe0;}
}
unless(defined(&IOASIC_BUFF3)) {
    sub IOASIC_BUFF3 () {	 &IOASIC_SLOT_1_START+0xf0;}
}
unless(defined(&IOASIC_CSR)) {
    sub IOASIC_CSR () {	 &IOASIC_SLOT_1_START+0x100;}
}
unless(defined(&IOASIC_INTR)) {
    sub IOASIC_INTR () {	 &IOASIC_SLOT_1_START+0x110;}
}
unless(defined(&IOASIC_IMSK)) {
    sub IOASIC_IMSK () {	 &IOASIC_SLOT_1_START+0x120;}
}
unless(defined(&IOASIC_CURADDR)) {
    sub IOASIC_CURADDR () {	 &IOASIC_SLOT_1_START+0x130;}
}
unless(defined(&IOASIC_ISDN_X_DATA)) {
    sub IOASIC_ISDN_X_DATA () {	 &IOASIC_SLOT_1_START+0x140;}
}
unless(defined(&IOASIC_ISDN_R_DATA)) {
    sub IOASIC_ISDN_R_DATA () {	 &IOASIC_SLOT_1_START+0x150;}
}
unless(defined(&IOASIC_LANCE_DECODE)) {
    sub IOASIC_LANCE_DECODE () {	 &IOASIC_SLOT_1_START+0x160;}
}
unless(defined(&IOASIC_SCSI_DECODE)) {
    sub IOASIC_SCSI_DECODE () {	 &IOASIC_SLOT_1_START+0x170;}
}
unless(defined(&IOASIC_SCC0_DECODE)) {
    sub IOASIC_SCC0_DECODE () {	 &IOASIC_SLOT_1_START+0x180;}
}
unless(defined(&IOASIC_SCC1_DECODE)) {
    sub IOASIC_SCC1_DECODE () {	 &IOASIC_SLOT_1_START+0x190;}
}
unless(defined(&IOASIC_FLOPPY_DECODE)) {
    sub IOASIC_FLOPPY_DECODE () {	 &IOASIC_SLOT_1_START+0x1a0;}
}
unless(defined(&IOASIC_SCSI_SCR)) {
    sub IOASIC_SCSI_SCR () {	 &IOASIC_SLOT_1_START+0x1b0;}
}
unless(defined(&IOASIC_SCSI_SDR0)) {
    sub IOASIC_SCSI_SDR0 () {	 &IOASIC_SLOT_1_START+0x1c0;}
}
unless(defined(&IOASIC_SCSI_SDR1)) {
    sub IOASIC_SCSI_SDR1 () {	 &IOASIC_SLOT_1_START+0x1d0;}
}
unless(defined(&IOASIC_CTR)) {
    sub IOASIC_CTR () {	 &IOASIC_SLOT_1_START+0x1e0;}
}
unless(defined(&IOASIC_CSR_DMAEN_T1)) {
    sub IOASIC_CSR_DMAEN_T1 () {	0x80000000;}
}
unless(defined(&IOASIC_CSR_DMAEN_R1)) {
    sub IOASIC_CSR_DMAEN_R1 () {	0x40000000;}
}
unless(defined(&IOASIC_CSR_DMAEN_T2)) {
    sub IOASIC_CSR_DMAEN_T2 () {	0x20000000;}
}
unless(defined(&IOASIC_CSR_DMAEN_R2)) {
    sub IOASIC_CSR_DMAEN_R2 () {	0x10000000;}
}
unless(defined(&IOASIC_CSR_FASTMODE)) {
    sub IOASIC_CSR_FASTMODE () {	0x8000000;}
}
unless(defined(&IOASIC_CSR_xxx)) {
    sub IOASIC_CSR_xxx () {	0x7800000;}
}
unless(defined(&IOASIC_CSR_DS_xxx)) {
    sub IOASIC_CSR_DS_xxx () {	0xf800000;}
}
unless(defined(&IOASIC_CSR_FLOPPY_DIR)) {
    sub IOASIC_CSR_FLOPPY_DIR () {	0x400000;}
}
unless(defined(&IOASIC_CSR_DMAEN_FLOPPY)) {
    sub IOASIC_CSR_DMAEN_FLOPPY () {	0x200000;}
}
unless(defined(&IOASIC_CSR_DMAEN_ISDN_T)) {
    sub IOASIC_CSR_DMAEN_ISDN_T () {	0x100000;}
}
unless(defined(&IOASIC_CSR_DMAEN_ISDN_R)) {
    sub IOASIC_CSR_DMAEN_ISDN_R () {	0x80000;}
}
unless(defined(&IOASIC_CSR_SCSI_DIR)) {
    sub IOASIC_CSR_SCSI_DIR () {	0x40000;}
}
unless(defined(&IOASIC_CSR_DMAEN_SCSI)) {
    sub IOASIC_CSR_DMAEN_SCSI () {	0x20000;}
}
unless(defined(&IOASIC_CSR_DMAEN_LANCE)) {
    sub IOASIC_CSR_DMAEN_LANCE () {	0x10000;}
}
unless(defined(&IOASIC_CSR_DIAGDN)) {
    sub IOASIC_CSR_DIAGDN () {	0x8000;}
}
unless(defined(&IOASIC_CSR_TXDIS_2)) {
    sub IOASIC_CSR_TXDIS_2 () {	0x4000;}
}
unless(defined(&IOASIC_CSR_TXDIS_1)) {
    sub IOASIC_CSR_TXDIS_1 () {	0x2000;}
}
unless(defined(&IOASIC_CSR_ISDN_ENABLE)) {
    sub IOASIC_CSR_ISDN_ENABLE () {	0x1000;}
}
unless(defined(&IOASIC_CSR_SCC_ENABLE)) {
    sub IOASIC_CSR_SCC_ENABLE () {	0x800;}
}
unless(defined(&IOASIC_CSR_RTC_ENABLE)) {
    sub IOASIC_CSR_RTC_ENABLE () {	0x400;}
}
unless(defined(&IOASIC_CSR_SCSI_ENABLE)) {
    sub IOASIC_CSR_SCSI_ENABLE () {	0x200;}
}
unless(defined(&IOASIC_CSR_LANCE_ENABLE)) {
    sub IOASIC_CSR_LANCE_ENABLE () {	0x100;}
}
unless(defined(&IOASIC_INTR_T1_PAGE_END)) {
    sub IOASIC_INTR_T1_PAGE_END () {	0x80000000;}
}
unless(defined(&IOASIC_INTR_T1_READ_E)) {
    sub IOASIC_INTR_T1_READ_E () {	0x40000000;}
}
unless(defined(&IOASIC_INTR_R1_HALF_PAGE)) {
    sub IOASIC_INTR_R1_HALF_PAGE () {	0x20000000;}
}
unless(defined(&IOASIC_INTR_R1_DMA_OVRUN)) {
    sub IOASIC_INTR_R1_DMA_OVRUN () {	0x10000000;}
}
unless(defined(&IOASIC_INTR_T2_PAGE_END)) {
    sub IOASIC_INTR_T2_PAGE_END () {	0x8000000;}
}
unless(defined(&IOASIC_INTR_T2_READ_E)) {
    sub IOASIC_INTR_T2_READ_E () {	0x4000000;}
}
unless(defined(&IOASIC_INTR_R2_HALF_PAGE)) {
    sub IOASIC_INTR_R2_HALF_PAGE () {	0x2000000;}
}
unless(defined(&IOASIC_INTR_R2_DMA_OVRUN)) {
    sub IOASIC_INTR_R2_DMA_OVRUN () {	0x1000000;}
}
unless(defined(&IOASIC_INTR_FLOPPY_DMA_E)) {
    sub IOASIC_INTR_FLOPPY_DMA_E () {	0x800000;}
}
unless(defined(&IOASIC_INTR_ISDN_TXLOAD)) {
    sub IOASIC_INTR_ISDN_TXLOAD () {	0x400000;}
}
unless(defined(&IOASIC_INTR_ISDN_RXLOAD)) {
    sub IOASIC_INTR_ISDN_RXLOAD () {	0x200000;}
}
unless(defined(&IOASIC_INTR_ISDN_OVRUN)) {
    sub IOASIC_INTR_ISDN_OVRUN () {	0x100000;}
}
unless(defined(&IOASIC_INTR_SCSI_PTR_LOAD)) {
    sub IOASIC_INTR_SCSI_PTR_LOAD () {	0x80000;}
}
unless(defined(&IOASIC_INTR_SCSI_OVRUN)) {
    sub IOASIC_INTR_SCSI_OVRUN () {	0x40000;}
}
unless(defined(&IOASIC_INTR_SCSI_READ_E)) {
    sub IOASIC_INTR_SCSI_READ_E () {	0x20000;}
}
unless(defined(&IOASIC_INTR_LANCE_READ_E)) {
    sub IOASIC_INTR_LANCE_READ_E () {	0x10000;}
}
unless(defined(&IOASIC_INTR_NVR_JUMPER)) {
    sub IOASIC_INTR_NVR_JUMPER () {	0x4000;}
}
unless(defined(&IOASIC_INTR_ISDN)) {
    sub IOASIC_INTR_ISDN () {	0x2000;}
}
unless(defined(&IOASIC_INTR_NRMOD_JUMPER)) {
    sub IOASIC_INTR_NRMOD_JUMPER () {	0x400;}
}
unless(defined(&IOASIC_INTR_SEC_CON)) {
    sub IOASIC_INTR_SEC_CON () {	0x200;}
}
unless(defined(&IOASIC_INTR_SCSI)) {
    sub IOASIC_INTR_SCSI () {	0x200;}
}
unless(defined(&IOASIC_INTR_LANCE)) {
    sub IOASIC_INTR_LANCE () {	0x100;}
}
unless(defined(&IOASIC_INTR_SCC_1)) {
    sub IOASIC_INTR_SCC_1 () {	0x80;}
}
unless(defined(&IOASIC_INTR_SCC_0)) {
    sub IOASIC_INTR_SCC_0 () {	0x40;}
}
unless(defined(&IOASIC_INTR_ALT_CON)) {
    sub IOASIC_INTR_ALT_CON () {	0x8;}
}
unless(defined(&IOASIC_INTR_300_OPT1)) {
    sub IOASIC_INTR_300_OPT1 () {	0x8;}
}
unless(defined(&IOASIC_INTR_300_OPT0)) {
    sub IOASIC_INTR_300_OPT0 () {	0x4;}
}
unless(defined(&IOASIC_DMA_ADDR)) {
    sub IOASIC_DMA_ADDR {
	my($p) = @_;
	eval q((((($p) << 3) & ~0x1f) | ((($p) >> 29) & 0x1f)));
    }
}
unless(defined(&IOASIC_DMA_BLOCKSIZE)) {
    sub IOASIC_DMA_BLOCKSIZE () {	0x1000;}
}
unless(defined(&IOASIC_SCR_STATUS)) {
    sub IOASIC_SCR_STATUS () {	0x4;}
}
unless(defined(&IOASIC_SCR_WORD)) {
    sub IOASIC_SCR_WORD () {	0x3;}
}
unless(defined(&IOASIC_DECODE_HW_ADDRESS)) {
    sub IOASIC_DECODE_HW_ADDRESS () {	0x3f0;}
}
unless(defined(&IOASIC_DECODE_CHIP_SELECT)) {
    sub IOASIC_DECODE_CHIP_SELECT () {	0xf;}
}
unless(defined(&IOASIC_SYS_ETHER_ADDRESS)) {
    sub IOASIC_SYS_ETHER_ADDRESS {
	my($base) = @_;
	eval q((($base) +  &IOASIC_SLOT_2_START));
    }
}
unless(defined(&IOASIC_SYS_LANCE)) {
    sub IOASIC_SYS_LANCE {
	my($base) = @_;
	eval q((($base) +  &IOASIC_SLOT_3_START));
    }
}
1;
