require '_h2ph_pre.ph';

no warnings 'redefine';

unless(defined(&_DEV_PCI_CMPCIREG_H_)) {
    eval 'sub _DEV_PCI_CMPCIREG_H_ () {1;}' unless defined(&_DEV_PCI_CMPCIREG_H_);
    eval 'sub CMPCI_PCI_IOBASEREG () {( &PCI_MAPREG_START);}' unless defined(&CMPCI_PCI_IOBASEREG);
    eval 'sub CMPCI_REG_FUNC_0 () {0x;}' unless defined(&CMPCI_REG_FUNC_0);
    eval 'sub CMPCI_REG_CH0_DIR () {0x1;}' unless defined(&CMPCI_REG_CH0_DIR);
    eval 'sub CMPCI_REG_CH1_DIR () {0x2;}' unless defined(&CMPCI_REG_CH1_DIR);
    eval 'sub CMPCI_REG_CH0_PAUSE () {0x4;}' unless defined(&CMPCI_REG_CH0_PAUSE);
    eval 'sub CMPCI_REG_CH1_PAUSE () {0x8;}' unless defined(&CMPCI_REG_CH1_PAUSE);
    eval 'sub CMPCI_REG_CH0_ENABLE () {0x10000;}' unless defined(&CMPCI_REG_CH0_ENABLE);
    eval 'sub CMPCI_REG_CH1_ENABLE () {0x20000;}' unless defined(&CMPCI_REG_CH1_ENABLE);
    eval 'sub CMPCI_REG_CH0_RESET () {0x40000;}' unless defined(&CMPCI_REG_CH0_RESET);
    eval 'sub CMPCI_REG_CH1_RESET () {0x80000;}' unless defined(&CMPCI_REG_CH1_RESET);
    eval 'sub CMPCI_REG_FUNC_1 () {0x4;}' unless defined(&CMPCI_REG_FUNC_1);
    eval 'sub CMPCI_REG_JOY_ENABLE () {0x2;}' unless defined(&CMPCI_REG_JOY_ENABLE);
    eval 'sub CMPCI_REG_UART_ENABLE () {0x4;}' unless defined(&CMPCI_REG_UART_ENABLE);
    eval 'sub CMPCI_REG_LEGACY_ENABLE () {0x8;}' unless defined(&CMPCI_REG_LEGACY_ENABLE);
    eval 'sub CMPCI_REG_BREQ () {0x10;}' unless defined(&CMPCI_REG_BREQ);
    eval 'sub CMPCI_REG_MCBINTR_ENABLE () {0x20;}' unless defined(&CMPCI_REG_MCBINTR_ENABLE);
    eval 'sub CMPCI_REG_SPDIFOUT_DAC () {0x40;}' unless defined(&CMPCI_REG_SPDIFOUT_DAC);
    eval 'sub CMPCI_REG_SPDIF_LOOP () {0x80;}' unless defined(&CMPCI_REG_SPDIF_LOOP);
    eval 'sub CMPCI_REG_SPDIF0_ENABLE () {0x100;}' unless defined(&CMPCI_REG_SPDIF0_ENABLE);
    eval 'sub CMPCI_REG_SPDIF1_ENABLE () {0x200;}' unless defined(&CMPCI_REG_SPDIF1_ENABLE);
    eval 'sub CMPCI_REG_DAC_FS_SHIFT () {10;}' unless defined(&CMPCI_REG_DAC_FS_SHIFT);
    eval 'sub CMPCI_REG_DAC_FS_MASK () {0x7;}' unless defined(&CMPCI_REG_DAC_FS_MASK);
    eval 'sub CMPCI_REG_ADC_FS_SHIFT () {13;}' unless defined(&CMPCI_REG_ADC_FS_SHIFT);
    eval 'sub CMPCI_REG_ADC_FS_MASK () {0x7;}' unless defined(&CMPCI_REG_ADC_FS_MASK);
    eval 'sub CMPCI_REG_CHANNEL_FORMAT () {0x8;}' unless defined(&CMPCI_REG_CHANNEL_FORMAT);
    eval 'sub CMPCI_REG_SPDIN_PHASE () {0x80;}' unless defined(&CMPCI_REG_SPDIN_PHASE);
    eval 'sub CMPCI_REG_CH0_FORMAT_SHIFT () {0;}' unless defined(&CMPCI_REG_CH0_FORMAT_SHIFT);
    eval 'sub CMPCI_REG_CH0_FORMAT_MASK () {0x3;}' unless defined(&CMPCI_REG_CH0_FORMAT_MASK);
    eval 'sub CMPCI_REG_CH1_FORMAT_SHIFT () {2;}' unless defined(&CMPCI_REG_CH1_FORMAT_SHIFT);
    eval 'sub CMPCI_REG_CH1_FORMAT_MASK () {0x3;}' unless defined(&CMPCI_REG_CH1_FORMAT_MASK);
    eval 'sub CMPCI_REG_FORMAT_MONO () {0x;}' unless defined(&CMPCI_REG_FORMAT_MONO);
    eval 'sub CMPCI_REG_FORMAT_STEREO () {0x1;}' unless defined(&CMPCI_REG_FORMAT_STEREO);
    eval 'sub CMPCI_REG_FORMAT_8BIT () {0x;}' unless defined(&CMPCI_REG_FORMAT_8BIT);
    eval 'sub CMPCI_REG_FORMAT_16BIT () {0x2;}' unless defined(&CMPCI_REG_FORMAT_16BIT);
    eval 'sub CMPCI_REG_INTR_CTRL () {0xc;}' unless defined(&CMPCI_REG_INTR_CTRL);
    eval 'sub CMPCI_REG_CH0_INTR_ENABLE () {0x10000;}' unless defined(&CMPCI_REG_CH0_INTR_ENABLE);
    eval 'sub CMPCI_REG_CH1_INTR_ENABLE () {0x20000;}' unless defined(&CMPCI_REG_CH1_INTR_ENABLE);
    eval 'sub CMPCI_REG_TDMA_INTR_ENABLE () {0x40000;}' unless defined(&CMPCI_REG_TDMA_INTR_ENABLE);
    eval 'sub CMPCI_REG_INTR_STATUS () {0x10;}' unless defined(&CMPCI_REG_INTR_STATUS);
    eval 'sub CMPCI_REG_CH0_INTR () {0x1;}' unless defined(&CMPCI_REG_CH0_INTR);
    eval 'sub CMPCI_REG_CH1_INTR () {0x2;}' unless defined(&CMPCI_REG_CH1_INTR);
    eval 'sub CMPCI_REG_CH0_BUSY () {0x4;}' unless defined(&CMPCI_REG_CH0_BUSY);
    eval 'sub CMPCI_REG_CH1_BUSY () {0x8;}' unless defined(&CMPCI_REG_CH1_BUSY);
    eval 'sub CMPCI_REG_LEGACY_STEREO () {0x10;}' unless defined(&CMPCI_REG_LEGACY_STEREO);
    eval 'sub CMPCI_REG_LEGACY_HDMA () {0x20;}' unless defined(&CMPCI_REG_LEGACY_HDMA);
    eval 'sub CMPCI_REG_DMASTAT () {0x40;}' unless defined(&CMPCI_REG_DMASTAT);
    eval 'sub CMPCI_REG_XDO46 () {0x80;}' unless defined(&CMPCI_REG_XDO46);
    eval 'sub CMPCI_REG_HTDMA_INTR () {0x4000;}' unless defined(&CMPCI_REG_HTDMA_INTR);
    eval 'sub CMPCI_REG_LTDMA_INTR () {0x8000;}' unless defined(&CMPCI_REG_LTDMA_INTR);
    eval 'sub CMPCI_REG_UART_INTR () {0x10000;}' unless defined(&CMPCI_REG_UART_INTR);
    eval 'sub CMPCI_REG_MCB_INTR () {0x4000000;}' unless defined(&CMPCI_REG_MCB_INTR);
    eval 'sub CMPCI_REG_VCO () {0x8000000;}' unless defined(&CMPCI_REG_VCO);
    eval 'sub CMPCI_REG_ANY_INTR () {0x80000000;}' unless defined(&CMPCI_REG_ANY_INTR);
    eval 'sub CMPCI_REG_LEGACY_CTRL () {0x14;}' unless defined(&CMPCI_REG_LEGACY_CTRL);
    eval 'sub CMPCI_REG_LEGACY_SPDIF_ENABLE () {0x200000;}' unless defined(&CMPCI_REG_LEGACY_SPDIF_ENABLE);
    eval 'sub CMPCI_REG_SPDIF_COPYRIGHT () {0x400000;}' unless defined(&CMPCI_REG_SPDIF_COPYRIGHT);
    eval 'sub CMPCI_REG_XSPDIF_ENABLE () {0x800000;}' unless defined(&CMPCI_REG_XSPDIF_ENABLE);
    eval 'sub CMPCI_REG_FMSEL_SHIFT () {24;}' unless defined(&CMPCI_REG_FMSEL_SHIFT);
    eval 'sub CMPCI_REG_FMSEL_MASK () {0x3;}' unless defined(&CMPCI_REG_FMSEL_MASK);
    eval 'sub CMPCI_REG_VSBSEL_SHIFT () {26;}' unless defined(&CMPCI_REG_VSBSEL_SHIFT);
    eval 'sub CMPCI_REG_VSBSEL_MASK () {0x3;}' unless defined(&CMPCI_REG_VSBSEL_MASK);
    eval 'sub CMPCI_REG_VMPUSEL_SHIFT () {29;}' unless defined(&CMPCI_REG_VMPUSEL_SHIFT);
    eval 'sub CMPCI_REG_VMPUSEL_MASK () {0x3;}' unless defined(&CMPCI_REG_VMPUSEL_MASK);
    eval 'sub CMPCI_REG_MISC () {0x18;}' unless defined(&CMPCI_REG_MISC);
    eval 'sub CMPCI_REG_2ND_SPDIFIN () {0x100;}' unless defined(&CMPCI_REG_2ND_SPDIFIN);
    eval 'sub CMPCI_REG_SPDIFOUT_48K () {0x8000;}' unless defined(&CMPCI_REG_SPDIFOUT_48K);
    eval 'sub CMPCI_REG_FM_ENABLE () {0x80000;}' unless defined(&CMPCI_REG_FM_ENABLE);
    eval 'sub CMPCI_REG_SPDFLOOPI () {0x100000;}' unless defined(&CMPCI_REG_SPDFLOOPI);
    eval 'sub CMPCI_REG_SPDIF48K () {0x1000000;}' unless defined(&CMPCI_REG_SPDIF48K);
    eval 'sub CMPCI_REG_5V () {0x2000000;}' unless defined(&CMPCI_REG_5V);
    eval 'sub CMPCI_REG_N4SPK3D () {0x4000000;}' unless defined(&CMPCI_REG_N4SPK3D);
    eval 'sub CMPCI_REG_SBDATA () {0x22;}' unless defined(&CMPCI_REG_SBDATA);
    eval 'sub CMPCI_REG_SBADDR () {0x23;}' unless defined(&CMPCI_REG_SBADDR);
    eval 'sub CMPCI_SB16_MIXER_RESET () {0x;}' unless defined(&CMPCI_SB16_MIXER_RESET);
    eval 'sub CMPCI_SB16_MIXER_MASTER_L () {0x30;}' unless defined(&CMPCI_SB16_MIXER_MASTER_L);
    eval 'sub CMPCI_SB16_MIXER_MASTER_R () {0x31;}' unless defined(&CMPCI_SB16_MIXER_MASTER_R);
    eval 'sub CMPCI_SB16_MIXER_VOICE_L () {0x32;}' unless defined(&CMPCI_SB16_MIXER_VOICE_L);
    eval 'sub CMPCI_SB16_MIXER_VOICE_R () {0x33;}' unless defined(&CMPCI_SB16_MIXER_VOICE_R);
    eval 'sub CMPCI_SB16_MIXER_FM_L () {0x34;}' unless defined(&CMPCI_SB16_MIXER_FM_L);
    eval 'sub CMPCI_SB16_MIXER_FM_R () {0x35;}' unless defined(&CMPCI_SB16_MIXER_FM_R);
    eval 'sub CMPCI_SB16_MIXER_CDDA_L () {0x36;}' unless defined(&CMPCI_SB16_MIXER_CDDA_L);
    eval 'sub CMPCI_SB16_MIXER_CDDA_R () {0x37;}' unless defined(&CMPCI_SB16_MIXER_CDDA_R);
    eval 'sub CMPCI_SB16_MIXER_LINE_L () {0x38;}' unless defined(&CMPCI_SB16_MIXER_LINE_L);
    eval 'sub CMPCI_SB16_MIXER_LINE_R () {0x39;}' unless defined(&CMPCI_SB16_MIXER_LINE_R);
    eval 'sub CMPCI_SB16_MIXER_MIC () {0x3a;}' unless defined(&CMPCI_SB16_MIXER_MIC);
    eval 'sub CMPCI_SB16_MIXER_VALBITS () {5;}' unless defined(&CMPCI_SB16_MIXER_VALBITS);
    eval 'sub CMPCI_SB16_MIXER_SPEAKER () {0x3b;}' unless defined(&CMPCI_SB16_MIXER_SPEAKER);
    eval 'sub CMPCI_SB16_MIXER_SPEAKER_VALBITS () {2;}' unless defined(&CMPCI_SB16_MIXER_SPEAKER_VALBITS);
    eval 'sub CMPCI_SB16_MIXER_OUTMIX () {0x3c;}' unless defined(&CMPCI_SB16_MIXER_OUTMIX);
    eval 'sub CMPCI_SB16_SW_MIC () {0x1;}' unless defined(&CMPCI_SB16_SW_MIC);
    eval 'sub CMPCI_SB16_SW_CD_R () {0x2;}' unless defined(&CMPCI_SB16_SW_CD_R);
    eval 'sub CMPCI_SB16_SW_CD_L () {0x4;}' unless defined(&CMPCI_SB16_SW_CD_L);
    eval 'sub CMPCI_SB16_SW_CD () {( &CMPCI_SB16_SW_CD_L| &CMPCI_SB16_SW_CD_R);}' unless defined(&CMPCI_SB16_SW_CD);
    eval 'sub CMPCI_SB16_SW_LINE_R () {0x8;}' unless defined(&CMPCI_SB16_SW_LINE_R);
    eval 'sub CMPCI_SB16_SW_LINE_L () {0x10;}' unless defined(&CMPCI_SB16_SW_LINE_L);
    eval 'sub CMPCI_SB16_SW_LINE () {( &CMPCI_SB16_SW_LINE_L| &CMPCI_SB16_SW_LINE_R);}' unless defined(&CMPCI_SB16_SW_LINE);
    eval 'sub CMPCI_SB16_SW_FM_R () {0x20;}' unless defined(&CMPCI_SB16_SW_FM_R);
    eval 'sub CMPCI_SB16_SW_FM_L () {0x40;}' unless defined(&CMPCI_SB16_SW_FM_L);
    eval 'sub CMPCI_SB16_SW_FM () {( &CMPCI_SB16_SW_FM_L| &CMPCI_SB16_SW_FM_R);}' unless defined(&CMPCI_SB16_SW_FM);
    eval 'sub CMPCI_SB16_MIXER_ADCMIX_L () {0x3d;}' unless defined(&CMPCI_SB16_MIXER_ADCMIX_L);
    eval 'sub CMPCI_SB16_MIXER_ADCMIX_R () {0x3e;}' unless defined(&CMPCI_SB16_MIXER_ADCMIX_R);
    eval 'sub CMPCI_SB16_MIXER_FM_SRC_R () {0x20;}' unless defined(&CMPCI_SB16_MIXER_FM_SRC_R);
    eval 'sub CMPCI_SB16_MIXER_LINE_SRC_R () {0x8;}' unless defined(&CMPCI_SB16_MIXER_LINE_SRC_R);
    eval 'sub CMPCI_SB16_MIXER_CD_SRC_R () {0x2;}' unless defined(&CMPCI_SB16_MIXER_CD_SRC_R);
    eval 'sub CMPCI_SB16_MIXER_MIC_SRC () {0x1;}' unless defined(&CMPCI_SB16_MIXER_MIC_SRC);
    eval 'sub CMPCI_SB16_MIXER_SRC_R_TO_L {
        my($v) = @_;
	    eval q((($v) << 1));
    }' unless defined(&CMPCI_SB16_MIXER_SRC_R_TO_L);
    eval 'sub CMPCI_SB16_MIXER_L_TO_R {
        my($addr) = @_;
	    eval q((($addr)+1));
    }' unless defined(&CMPCI_SB16_MIXER_L_TO_R);
    eval 'sub CMPCI_ADJUST_MIC_GAIN {
        my($sc, $x) = @_;
	    eval q( &cmpci_adjust(($x), 0xf8));
    }' unless defined(&CMPCI_ADJUST_MIC_GAIN);
    eval 'sub CMPCI_ADJUST_GAIN {
        my($sc, $x) = @_;
	    eval q( &cmpci_adjust(($x), 0xf8));
    }' unless defined(&CMPCI_ADJUST_GAIN);
    eval 'sub CMPCI_ADJUST_2_GAIN {
        my($sc, $x) = @_;
	    eval q( &cmpci_adjust(($x), 0xc0));
    }' unless defined(&CMPCI_ADJUST_2_GAIN);
    eval 'sub CMPCI_REG_MIXER24 () {0x24;}' unless defined(&CMPCI_REG_MIXER24);
    eval 'sub CMPCI_REG_SPDIN_MONITOR () {0x1;}' unless defined(&CMPCI_REG_SPDIN_MONITOR);
    eval 'sub CMPCI_REG_SURROUND () {0x2;}' unless defined(&CMPCI_REG_SURROUND);
    eval 'sub CMPCI_REG_INDIVIDUAL () {0x20;}' unless defined(&CMPCI_REG_INDIVIDUAL);
    eval 'sub CMPCI_REG_REVERSE_FR () {0x10;}' unless defined(&CMPCI_REG_REVERSE_FR);
    eval 'sub CMPCI_REG_FMMUTE () {0x80;}' unless defined(&CMPCI_REG_FMMUTE);
    eval 'sub CMPCI_REG_WSMUTE () {0x40;}' unless defined(&CMPCI_REG_WSMUTE);
    eval 'sub CMPCI_REG_WAVEINL () {0x8;}' unless defined(&CMPCI_REG_WAVEINL);
    eval 'sub CMPCI_REG_WAVEINR () {0x4;}' unless defined(&CMPCI_REG_WAVEINR);
    eval 'sub CMPCI_REG_MIXER25 () {0x25;}' unless defined(&CMPCI_REG_MIXER25);
    eval 'sub CMPCI_REG_RAUXREN () {0x80;}' unless defined(&CMPCI_REG_RAUXREN);
    eval 'sub CMPCI_REG_RAUXLEN () {0x40;}' unless defined(&CMPCI_REG_RAUXLEN);
    eval 'sub CMPCI_REG_VAUXRM () {0x20;}' unless defined(&CMPCI_REG_VAUXRM);
    eval 'sub CMPCI_REG_VAUXLM () {0x10;}' unless defined(&CMPCI_REG_VAUXLM);
    eval 'sub CMPCI_REG_VADMIC () {0xe;}' unless defined(&CMPCI_REG_VADMIC);
    eval 'sub CMPCI_REG_MICGAINZ () {0x1;}' unless defined(&CMPCI_REG_MICGAINZ);
    eval 'sub CMPCI_ADJUST_ADMIC_GAIN {
        my($sc, $x) = @_;
	    eval q(( &cmpci_adjust(($x), 0xe0) >> 5));
    }' unless defined(&CMPCI_ADJUST_ADMIC_GAIN);
    eval 'sub CMPCI_REG_ADMIC_VALBITS () {3;}' unless defined(&CMPCI_REG_ADMIC_VALBITS);
    eval 'sub CMPCI_REG_ADMIC_MASK () {0x7;}' unless defined(&CMPCI_REG_ADMIC_MASK);
    eval 'sub CMPCI_REG_ADMIC_SHIFT () {0x1;}' unless defined(&CMPCI_REG_ADMIC_SHIFT);
    eval 'sub CMPCI_REG_MIXER_AUX () {0x26;}' unless defined(&CMPCI_REG_MIXER_AUX);
    eval 'sub CMPCI_ADJUST_AUX_GAIN {
        my($sc, $l, $r) = @_;
	    eval q(( &cmpci_adjust(($l), 0xc0) >> 4|  &cmpci_adjust(($r), 0xc0)));
    }' unless defined(&CMPCI_ADJUST_AUX_GAIN);
    eval 'sub CMPCI_REG_AUX_VALBITS () {4;}' unless defined(&CMPCI_REG_AUX_VALBITS);
    eval 'sub CMPCI_REG_MPU_BASE () {0x40;}' unless defined(&CMPCI_REG_MPU_BASE);
    eval 'sub CMPCI_REG_MPU_SIZE () {0x10;}' unless defined(&CMPCI_REG_MPU_SIZE);
    eval 'sub CMPCI_REG_FM_BASE () {0x50;}' unless defined(&CMPCI_REG_FM_BASE);
    eval 'sub CMPCI_REG_FM_SIZE () {0x10;}' unless defined(&CMPCI_REG_FM_SIZE);
    eval 'sub CMPCI_REG_DMA0_BASE () {0x80;}' unless defined(&CMPCI_REG_DMA0_BASE);
    eval 'sub CMPCI_REG_DMA0_BYTES () {0x84;}' unless defined(&CMPCI_REG_DMA0_BYTES);
    eval 'sub CMPCI_REG_DMA0_SAMPLES () {0x86;}' unless defined(&CMPCI_REG_DMA0_SAMPLES);
    eval 'sub CMPCI_REG_DMA1_BASE () {0x88;}' unless defined(&CMPCI_REG_DMA1_BASE);
    eval 'sub CMPCI_REG_DMA1_BYTES () {0x8c;}' unless defined(&CMPCI_REG_DMA1_BYTES);
    eval 'sub CMPCI_REG_DMA1_SAMPLES () {0x8e;}' unless defined(&CMPCI_REG_DMA1_SAMPLES);
    eval 'sub CMPCI_REG_RATE_5512 () {0;}' unless defined(&CMPCI_REG_RATE_5512);
    eval 'sub CMPCI_REG_RATE_11025 () {1;}' unless defined(&CMPCI_REG_RATE_11025);
    eval 'sub CMPCI_REG_RATE_22050 () {2;}' unless defined(&CMPCI_REG_RATE_22050);
    eval 'sub CMPCI_REG_RATE_44100 () {3;}' unless defined(&CMPCI_REG_RATE_44100);
    eval 'sub CMPCI_REG_RATE_8000 () {4;}' unless defined(&CMPCI_REG_RATE_8000);
    eval 'sub CMPCI_REG_RATE_16000 () {5;}' unless defined(&CMPCI_REG_RATE_16000);
    eval 'sub CMPCI_REG_RATE_32000 () {6;}' unless defined(&CMPCI_REG_RATE_32000);
    eval 'sub CMPCI_REG_RATE_48000 () {7;}' unless defined(&CMPCI_REG_RATE_48000);
    eval 'sub CMPCI_REG_NUMRATE () {8;}' unless defined(&CMPCI_REG_NUMRATE);
}
1;
