require '_h2ph_pre.ph';

no warnings 'redefine';

unless(defined(&_DEV_PCI_PCIIDE_OPTI_REG_H_)) {
    eval 'sub _DEV_PCI_PCIIDE_OPTI_REG_H_ () {1;}' unless defined(&_DEV_PCI_PCIIDE_OPTI_REG_H_);
    eval 'sub OPTI_REG_INIT_CONTROL () {0x40;}' unless defined(&OPTI_REG_INIT_CONTROL);
    eval 'sub OPTI_INIT_CONTROL_MODE_PIO_0 () {0;}' unless defined(&OPTI_INIT_CONTROL_MODE_PIO_0);
    eval 'sub OPTI_INIT_CONTROL_MODE_PIO_1 () {2;}' unless defined(&OPTI_INIT_CONTROL_MODE_PIO_1);
    eval 'sub OPTI_INIT_CONTROL_MODE_PIO_2 () {1;}' unless defined(&OPTI_INIT_CONTROL_MODE_PIO_2);
    eval 'sub OPTI_INIT_CONTROL_MODE_PIO_3 () {3;}' unless defined(&OPTI_INIT_CONTROL_MODE_PIO_3);
    eval 'sub OPTI_INIT_CONTROL_ADDR_RELOC () {(1 << 2);}' unless defined(&OPTI_INIT_CONTROL_ADDR_RELOC);
    eval 'sub OPTI_INIT_CONTROL_CH2_ENABLE () {0;}' unless defined(&OPTI_INIT_CONTROL_CH2_ENABLE);
    eval 'sub OPTI_INIT_CONTROL_CH2_DISABLE () {(1 << 3);}' unless defined(&OPTI_INIT_CONTROL_CH2_DISABLE);
    eval 'sub OPTI_INIT_CONTROL_FIFO_16 () {0;}' unless defined(&OPTI_INIT_CONTROL_FIFO_16);
    eval 'sub OPTI_INIT_CONTROL_FIFO_32 () {(1 << 5);}' unless defined(&OPTI_INIT_CONTROL_FIFO_32);
    eval 'sub OPTI_INIT_CONTROL_FIFO_REQ_32 () {0;}' unless defined(&OPTI_INIT_CONTROL_FIFO_REQ_32);
    eval 'sub OPTI_INIT_CONTROL_FIFO_REQ_30 () {(1 << 6);}' unless defined(&OPTI_INIT_CONTROL_FIFO_REQ_30);
    eval 'sub OPTI_INIT_CONTROL_FIFO_REQ_28 () {(2 << 6);}' unless defined(&OPTI_INIT_CONTROL_FIFO_REQ_28);
    eval 'sub OPTI_INIT_CONTROL_FIFO_REQ_26 () {(3 << 6);}' unless defined(&OPTI_INIT_CONTROL_FIFO_REQ_26);
    eval 'sub OPTI_REG_ENH_FEAT () {0x42;}' unless defined(&OPTI_REG_ENH_FEAT);
    eval 'sub OPTI_ENH_FEAT_X111_ENABLE () {(1 << 1);}' unless defined(&OPTI_ENH_FEAT_X111_ENABLE);
    eval 'sub OPTI_ENH_FEAT_CONCURRENT_MAST () {(1 << 2);}' unless defined(&OPTI_ENH_FEAT_CONCURRENT_MAST);
    eval 'sub OPTI_ENH_FEAT_PCI_INVALIDATE () {(1 << 3);}' unless defined(&OPTI_ENH_FEAT_PCI_INVALIDATE);
    eval 'sub OPTI_ENH_FEAT_IDE_CONCUR () {(1 << 4);}' unless defined(&OPTI_ENH_FEAT_IDE_CONCUR);
    eval 'sub OPTI_ENH_FEAT_SLAVE_FIFO_ISA () {(1 << 5);}' unless defined(&OPTI_ENH_FEAT_SLAVE_FIFO_ISA);
    eval 'sub OPTI_REG_ENH_MODE () {0x43;}' unless defined(&OPTI_REG_ENH_MODE);
    eval 'sub OPTI_ENH_MODE_MASK {
        my($c,$d) = @_;
	    eval q((3 << ((($c) * 4) + (($d) * 2))));
    }' unless defined(&OPTI_ENH_MODE_MASK);
    eval 'sub OPTI_ENH_MODE_USE_TIMING {
        my($c,$d) = @_;
	    eval q(0);
    }' unless defined(&OPTI_ENH_MODE_USE_TIMING);
    eval 'sub OPTI_ENH_MODE {
        my($c,$d,$m) = @_;
	    eval q((($m) << ((($c) * 4) + (($d) * 2))));
    }' unless defined(&OPTI_ENH_MODE);
    eval 'sub OPTI_REG_READ_CYCLE_TIMING () {0x;}' unless defined(&OPTI_REG_READ_CYCLE_TIMING);
    eval 'sub OPTI_REG_WRITE_CYCLE_TIMING () {0x1;}' unless defined(&OPTI_REG_WRITE_CYCLE_TIMING);
    eval 'sub OPTI_RECOVERY_TIME_SHIFT () {0;}' unless defined(&OPTI_RECOVERY_TIME_SHIFT);
    eval 'sub OPTI_PULSE_WIDTH_SHIFT () {4;}' unless defined(&OPTI_PULSE_WIDTH_SHIFT);
    eval 'sub OPTI_REG_CONTROL () {0x3;}' unless defined(&OPTI_REG_CONTROL);
    eval 'sub OPTI_CONTROL_DISABLE () {0x11;}' unless defined(&OPTI_CONTROL_DISABLE);
    eval 'sub OPTI_CONTROL_ENABLE () {0x95;}' unless defined(&OPTI_CONTROL_ENABLE);
    eval 'sub OPTI_REG_STRAP () {0x5;}' unless defined(&OPTI_REG_STRAP);
    eval 'sub OPTI_STRAP_PCI_SPEED_MASK () {0x1;}' unless defined(&OPTI_STRAP_PCI_SPEED_MASK);
    eval 'sub OPTI_STRAP_PCI_33 () {0;}' unless defined(&OPTI_STRAP_PCI_33);
    eval 'sub OPTI_STRAP_PCI_25 () {1;}' unless defined(&OPTI_STRAP_PCI_25);
    eval 'sub OPTI_REG_MISC () {0x6;}' unless defined(&OPTI_REG_MISC);
    eval 'sub OPTI_MISC_INDEX {
        my($d) = @_;
	    eval q((($d)));
    }' unless defined(&OPTI_MISC_INDEX);
    eval 'sub OPTI_MISC_INDEX_MASK () {0x1;}' unless defined(&OPTI_MISC_INDEX_MASK);
    eval 'sub OPTI_MISC_DELAY_MASK () {0x7;}' unless defined(&OPTI_MISC_DELAY_MASK);
    eval 'sub OPTI_MISC_DELAY_SHIFT () {1;}' unless defined(&OPTI_MISC_DELAY_SHIFT);
    eval 'sub OPTI_MISC_ADDR_SETUP_MASK () {0x3;}' unless defined(&OPTI_MISC_ADDR_SETUP_MASK);
    eval 'sub OPTI_MISC_ADDR_SETUP_SHIFT () {4;}' unless defined(&OPTI_MISC_ADDR_SETUP_SHIFT);
    eval 'sub OPTI_MISC_READ_PREFETCH_ENABLE () {(1 << 6);}' unless defined(&OPTI_MISC_READ_PREFETCH_ENABLE);
    eval 'sub OPTI_MISC_ADDR_SETUP_MASK () {0x3;}' unless defined(&OPTI_MISC_ADDR_SETUP_MASK);
    eval 'sub OPTI_MISC_WRITE_MASK () {0x7f;}' unless defined(&OPTI_MISC_WRITE_MASK);
}
1;
