require '_h2ph_pre.ph';

no warnings 'redefine';

unless(defined(&_MIPS_CPU_H_)) {
    eval 'sub _MIPS_CPU_H_ () {1;}' unless defined(&_MIPS_CPU_H_);
    require 'machine/psl.ph';
    if(defined(&__LP64__)) {
	eval 'sub KSEG0_BASE () {0xffffffff80000000;}' unless defined(&KSEG0_BASE);
	eval 'sub KSEG1_BASE () {0xffffffffa0000000;}' unless defined(&KSEG1_BASE);
	eval 'sub KSSEG_BASE () {0xffffffffc0000000;}' unless defined(&KSSEG_BASE);
	eval 'sub KSEG3_BASE () {0xffffffffe0000000;}' unless defined(&KSEG3_BASE);
	eval 'sub XKSEG0_BASE () {0x9800000000000000;}' unless defined(&XKSEG0_BASE);
	eval 'sub XKSEG1_BASE () {0x9000000000000000;}' unless defined(&XKSEG1_BASE);
    } else {
	eval 'sub KSEG0_BASE () {0x80000000;}' unless defined(&KSEG0_BASE);
	eval 'sub KSEG1_BASE () {0xa0000000;}' unless defined(&KSEG1_BASE);
	eval 'sub KSSEG_BASE () {0xc0000000;}' unless defined(&KSSEG_BASE);
	eval 'sub KSEG3_BASE () {0xe0000000;}' unless defined(&KSEG3_BASE);
    }
    eval 'sub KSEG_SIZE () {0x20000000;}' unless defined(&KSEG_SIZE);
    eval 'sub KSEG0_TO_PHYS {
        my($x) = @_;
	    eval q((($x) & 0x1fffffff));
    }' unless defined(&KSEG0_TO_PHYS);
    eval 'sub KSEG1_TO_PHYS {
        my($x) = @_;
	    eval q((($x) & 0x1fffffff));
    }' unless defined(&KSEG1_TO_PHYS);
    eval 'sub PHYS_TO_KSEG0 {
        my($x) = @_;
	    eval q((($x) |  &KSEG0_BASE));
    }' unless defined(&PHYS_TO_KSEG0);
    eval 'sub PHYS_TO_KSEG1 {
        my($x) = @_;
	    eval q((($x) |  &KSEG1_BASE));
    }' unless defined(&PHYS_TO_KSEG1);
    eval 'sub PHYS_TO_KSEG3 {
        my($x) = @_;
	    eval q((($x) |  &KSEG3_BASE));
    }' unless defined(&PHYS_TO_KSEG3);
    if(defined(&_KERNEL)) {
	eval 'sub SR_XX () {0x80000000;}' unless defined(&SR_XX);
	eval 'sub SR_COP_USABILITY () {0x30000000;}' unless defined(&SR_COP_USABILITY);
	eval 'sub SR_COP_0_BIT () {0x10000000;}' unless defined(&SR_COP_0_BIT);
	eval 'sub SR_COP_1_BIT () {0x20000000;}' unless defined(&SR_COP_1_BIT);
	eval 'sub SR_RP () {0x8000000;}' unless defined(&SR_RP);
	eval 'sub SR_FR_32 () {0x4000000;}' unless defined(&SR_FR_32);
	eval 'sub SR_RE () {0x2000000;}' unless defined(&SR_RE);
	eval 'sub SR_DSD () {0x1000000;}' unless defined(&SR_DSD);
	eval 'sub SR_BOOT_EXC_VEC () {0x400000;}' unless defined(&SR_BOOT_EXC_VEC);
	eval 'sub SR_TLB_SHUTDOWN () {0x200000;}' unless defined(&SR_TLB_SHUTDOWN);
	eval 'sub SR_SOFT_RESET () {0x100000;}' unless defined(&SR_SOFT_RESET);
	eval 'sub SR_DIAG_CH () {0x40000;}' unless defined(&SR_DIAG_CH);
	eval 'sub SR_DIAG_CE () {0x20000;}' unless defined(&SR_DIAG_CE);
	eval 'sub SR_DIAG_DE () {0x10000;}' unless defined(&SR_DIAG_DE);
	eval 'sub SR_KX () {0x80;}' unless defined(&SR_KX);
	eval 'sub SR_SX () {0x40;}' unless defined(&SR_SX);
	eval 'sub SR_UX () {0x20;}' unless defined(&SR_UX);
	eval 'sub SR_KSU_MASK () {0x18;}' unless defined(&SR_KSU_MASK);
	eval 'sub SR_KSU_USER () {0x10;}' unless defined(&SR_KSU_USER);
	eval 'sub SR_KSU_SUPER () {0x8;}' unless defined(&SR_KSU_SUPER);
	eval 'sub SR_KSU_KERNEL () {0x;}' unless defined(&SR_KSU_KERNEL);
	eval 'sub SR_ERL () {0x4;}' unless defined(&SR_ERL);
	eval 'sub SR_EXL () {0x2;}' unless defined(&SR_EXL);
	eval 'sub SR_INT_ENAB () {0x1;}' unless defined(&SR_INT_ENAB);
	eval 'sub SR_INT_MASK () {0xff00;}' unless defined(&SR_INT_MASK);
	eval 'sub SOFT_INT_MASK_0 () {0x100;}' unless defined(&SOFT_INT_MASK_0);
	eval 'sub SOFT_INT_MASK_1 () {0x200;}' unless defined(&SOFT_INT_MASK_1);
	eval 'sub SR_INT_MASK_0 () {0x400;}' unless defined(&SR_INT_MASK_0);
	eval 'sub SR_INT_MASK_1 () {0x800;}' unless defined(&SR_INT_MASK_1);
	eval 'sub SR_INT_MASK_2 () {0x1000;}' unless defined(&SR_INT_MASK_2);
	eval 'sub SR_INT_MASK_3 () {0x2000;}' unless defined(&SR_INT_MASK_3);
	eval 'sub SR_INT_MASK_4 () {0x4000;}' unless defined(&SR_INT_MASK_4);
	eval 'sub SR_INT_MASK_5 () {0x8000;}' unless defined(&SR_INT_MASK_5);
	eval 'sub IC_INT_MASK () {0x3f00;}' unless defined(&IC_INT_MASK);
	eval 'sub IC_INT_MASK_6 () {0x100;}' unless defined(&IC_INT_MASK_6);
	eval 'sub IC_INT_MASK_7 () {0x200;}' unless defined(&IC_INT_MASK_7);
	eval 'sub IC_INT_MASK_8 () {0x400;}' unless defined(&IC_INT_MASK_8);
	eval 'sub IC_INT_MASK_9 () {0x800;}' unless defined(&IC_INT_MASK_9);
	eval 'sub IC_INT_TIMR () {0x1000;}' unless defined(&IC_INT_TIMR);
	eval 'sub IC_INT_PERF () {0x2000;}' unless defined(&IC_INT_PERF);
	eval 'sub IC_INT_TE () {0x80;}' unless defined(&IC_INT_TE);
	eval 'sub ALL_INT_MASK () {(( &IC_INT_MASK << 8) |  &SR_INT_MASK);}' unless defined(&ALL_INT_MASK);
	eval 'sub SOFT_INT_MASK () {( &SOFT_INT_MASK_0 |  &SOFT_INT_MASK_1);}' unless defined(&SOFT_INT_MASK);
	eval 'sub HW_INT_MASK () {( &ALL_INT_MASK & ~ &SOFT_INT_MASK);}' unless defined(&HW_INT_MASK);
	eval 'sub CR_BR_DELAY () {0x80000000;}' unless defined(&CR_BR_DELAY);
	eval 'sub CR_COP_ERR () {0x30000000;}' unless defined(&CR_COP_ERR);
	eval 'sub CR_EXC_CODE () {0x7c;}' unless defined(&CR_EXC_CODE);
	eval 'sub CR_EXC_CODE_SHIFT () {2;}' unless defined(&CR_EXC_CODE_SHIFT);
	eval 'sub CR_IPEND () {0x3fff00;}' unless defined(&CR_IPEND);
	eval 'sub CR_INT_SOFT0 () {0x100;}' unless defined(&CR_INT_SOFT0);
	eval 'sub CR_INT_SOFT1 () {0x200;}' unless defined(&CR_INT_SOFT1);
	eval 'sub CR_INT_0 () {0x400;}' unless defined(&CR_INT_0);
	eval 'sub CR_INT_1 () {0x800;}' unless defined(&CR_INT_1);
	eval 'sub CR_INT_2 () {0x1000;}' unless defined(&CR_INT_2);
	eval 'sub CR_INT_3 () {0x2000;}' unless defined(&CR_INT_3);
	eval 'sub CR_INT_4 () {0x4000;}' unless defined(&CR_INT_4);
	eval 'sub CR_INT_5 () {0x8000;}' unless defined(&CR_INT_5);
	eval 'sub CR_INT_6 () {0x10000;}' unless defined(&CR_INT_6);
	eval 'sub CR_INT_7 () {0x20000;}' unless defined(&CR_INT_7);
	eval 'sub CR_INT_8 () {0x40000;}' unless defined(&CR_INT_8);
	eval 'sub CR_INT_9 () {0x80000;}' unless defined(&CR_INT_9);
	eval 'sub CR_INT_HARD () {0xffc00;}' unless defined(&CR_INT_HARD);
	eval 'sub CR_INT_TIMR () {0x100000;}' unless defined(&CR_INT_TIMR);
	eval 'sub CR_INT_PERF () {0x200000;}' unless defined(&CR_INT_PERF);
	eval 'sub CNTXT_PTE_BASE () {0xff800000;}' unless defined(&CNTXT_PTE_BASE);
	eval 'sub CNTXT_BAD_VPN2 () {0x7ffff0;}' unless defined(&CNTXT_BAD_VPN2);
	eval 'sub RESET_EXC_VEC () {( &KSEG0_BASE + 0x3fc00000);}' unless defined(&RESET_EXC_VEC);
	eval 'sub TLB_MISS_EXC_VEC () {( &KSEG0_BASE + 0x);}' unless defined(&TLB_MISS_EXC_VEC);
	eval 'sub XTLB_MISS_EXC_VEC () {( &KSEG0_BASE + 0x80);}' unless defined(&XTLB_MISS_EXC_VEC);
	eval 'sub CACHE_ERR_EXC_VEC () {( &KSEG0_BASE + 0x100);}' unless defined(&CACHE_ERR_EXC_VEC);
	eval 'sub GEN_EXC_VEC () {( &KSEG0_BASE + 0x180);}' unless defined(&GEN_EXC_VEC);
	eval 'sub COP_0_TLB_INDEX () {$0;}' unless defined(&COP_0_TLB_INDEX);
	eval 'sub COP_0_TLB_RANDOM () {$1;}' unless defined(&COP_0_TLB_RANDOM);
	eval 'sub COP_0_TLB_LO0 () {$2;}' unless defined(&COP_0_TLB_LO0);
	eval 'sub COP_0_TLB_LO1 () {$3;}' unless defined(&COP_0_TLB_LO1);
	eval 'sub COP_0_TLB_CONTEXT () {$4;}' unless defined(&COP_0_TLB_CONTEXT);
	eval 'sub COP_0_TLB_PG_MASK () {$5;}' unless defined(&COP_0_TLB_PG_MASK);
	eval 'sub COP_0_TLB_WIRED () {$6;}' unless defined(&COP_0_TLB_WIRED);
	eval 'sub COP_0_BAD_VADDR () {$8;}' unless defined(&COP_0_BAD_VADDR);
	eval 'sub COP_0_COUNT () {$9;}' unless defined(&COP_0_COUNT);
	eval 'sub COP_0_TLB_HI () {$10;}' unless defined(&COP_0_TLB_HI);
	eval 'sub COP_0_COMPARE () {$11;}' unless defined(&COP_0_COMPARE);
	eval 'sub COP_0_STATUS_REG () {$12;}' unless defined(&COP_0_STATUS_REG);
	eval 'sub COP_0_CAUSE_REG () {$13;}' unless defined(&COP_0_CAUSE_REG);
	eval 'sub COP_0_EXC_PC () {$14;}' unless defined(&COP_0_EXC_PC);
	eval 'sub COP_0_PRID () {$15;}' unless defined(&COP_0_PRID);
	eval 'sub COP_0_CONFIG () {$16;}' unless defined(&COP_0_CONFIG);
	eval 'sub COP_0_LLADDR () {$17;}' unless defined(&COP_0_LLADDR);
	eval 'sub COP_0_WATCH_LO () {$18;}' unless defined(&COP_0_WATCH_LO);
	eval 'sub COP_0_WATCH_HI () {$19;}' unless defined(&COP_0_WATCH_HI);
	eval 'sub COP_0_TLB_XCONTEXT () {$20;}' unless defined(&COP_0_TLB_XCONTEXT);
	eval 'sub COP_0_ECC () {$26;}' unless defined(&COP_0_ECC);
	eval 'sub COP_0_CACHE_ERR () {$27;}' unless defined(&COP_0_CACHE_ERR);
	eval 'sub COP_0_TAG_LO () {$28;}' unless defined(&COP_0_TAG_LO);
	eval 'sub COP_0_TAG_HI () {$29;}' unless defined(&COP_0_TAG_HI);
	eval 'sub COP_0_ERROR_PC () {$30;}' unless defined(&COP_0_ERROR_PC);
	eval 'sub COP_0_WATCH_1 () {$18;}' unless defined(&COP_0_WATCH_1);
	eval 'sub COP_0_WATCH_2 () {$19;}' unless defined(&COP_0_WATCH_2);
	eval 'sub COP_0_WATCH_M () {$24;}' unless defined(&COP_0_WATCH_M);
	eval 'sub COP_0_PC_COUNT () {$25;}' unless defined(&COP_0_PC_COUNT);
	eval 'sub COP_0_PC_CTRL () {$22;}' unless defined(&COP_0_PC_CTRL);
	eval 'sub COP_0_ICR () {$20;}' unless defined(&COP_0_ICR);
	eval 'sub BREAK_INSTR () {0xd;}' unless defined(&BREAK_INSTR);
	eval 'sub BREAK_VAL_MASK () {0x3ff0000;}' unless defined(&BREAK_VAL_MASK);
	eval 'sub BREAK_VAL_SHIFT () {16;}' unless defined(&BREAK_VAL_SHIFT);
	eval 'sub BREAK_KDB_VAL () {512;}' unless defined(&BREAK_KDB_VAL);
	eval 'sub BREAK_SSTEP_VAL () {513;}' unless defined(&BREAK_SSTEP_VAL);
	eval 'sub BREAK_BRKPT_VAL () {514;}' unless defined(&BREAK_BRKPT_VAL);
	eval 'sub BREAK_SOVER_VAL () {515;}' unless defined(&BREAK_SOVER_VAL);
	eval 'sub BREAK_DDB_VAL () {516;}' unless defined(&BREAK_DDB_VAL);
	eval 'sub BREAK_KDB () {( &BREAK_INSTR | ( &BREAK_KDB_VAL <<  &BREAK_VAL_SHIFT));}' unless defined(&BREAK_KDB);
	eval 'sub BREAK_SSTEP () {( &BREAK_INSTR | ( &BREAK_SSTEP_VAL <<  &BREAK_VAL_SHIFT));}' unless defined(&BREAK_SSTEP);
	eval 'sub BREAK_BRKPT () {( &BREAK_INSTR | ( &BREAK_BRKPT_VAL <<  &BREAK_VAL_SHIFT));}' unless defined(&BREAK_BRKPT);
	eval 'sub BREAK_SOVER () {( &BREAK_INSTR | ( &BREAK_SOVER_VAL <<  &BREAK_VAL_SHIFT));}' unless defined(&BREAK_SOVER);
	eval 'sub BREAK_DDB () {( &BREAK_INSTR | ( &BREAK_DDB_VAL <<  &BREAK_VAL_SHIFT));}' unless defined(&BREAK_DDB);
	eval 'sub MIN_CACHE_SIZE () {(16* 1024);}' unless defined(&MIN_CACHE_SIZE);
	eval 'sub MAX_CACHE_SIZE () {(256* 1024);}' unless defined(&MAX_CACHE_SIZE);
	eval 'sub FPC_ID () {$0;}' unless defined(&FPC_ID);
	eval 'sub FPC_CSR () {$31;}' unless defined(&FPC_CSR);
	eval 'sub FPC_ROUNDING_BITS () {0x3;}' unless defined(&FPC_ROUNDING_BITS);
	eval 'sub FPC_ROUND_RN () {0x;}' unless defined(&FPC_ROUND_RN);
	eval 'sub FPC_ROUND_RZ () {0x1;}' unless defined(&FPC_ROUND_RZ);
	eval 'sub FPC_ROUND_RP () {0x2;}' unless defined(&FPC_ROUND_RP);
	eval 'sub FPC_ROUND_RM () {0x3;}' unless defined(&FPC_ROUND_RM);
	eval 'sub FPC_STICKY_BITS () {0x7c;}' unless defined(&FPC_STICKY_BITS);
	eval 'sub FPC_STICKY_INEXACT () {0x4;}' unless defined(&FPC_STICKY_INEXACT);
	eval 'sub FPC_STICKY_UNDERFLOW () {0x8;}' unless defined(&FPC_STICKY_UNDERFLOW);
	eval 'sub FPC_STICKY_OVERFLOW () {0x10;}' unless defined(&FPC_STICKY_OVERFLOW);
	eval 'sub FPC_STICKY_DIV0 () {0x20;}' unless defined(&FPC_STICKY_DIV0);
	eval 'sub FPC_STICKY_INVALID () {0x40;}' unless defined(&FPC_STICKY_INVALID);
	eval 'sub FPC_ENABLE_BITS () {0xf80;}' unless defined(&FPC_ENABLE_BITS);
	eval 'sub FPC_ENABLE_INEXACT () {0x80;}' unless defined(&FPC_ENABLE_INEXACT);
	eval 'sub FPC_ENABLE_UNDERFLOW () {0x100;}' unless defined(&FPC_ENABLE_UNDERFLOW);
	eval 'sub FPC_ENABLE_OVERFLOW () {0x200;}' unless defined(&FPC_ENABLE_OVERFLOW);
	eval 'sub FPC_ENABLE_DIV0 () {0x400;}' unless defined(&FPC_ENABLE_DIV0);
	eval 'sub FPC_ENABLE_INVALID () {0x800;}' unless defined(&FPC_ENABLE_INVALID);
	eval 'sub FPC_EXCEPTION_BITS () {0x3f000;}' unless defined(&FPC_EXCEPTION_BITS);
	eval 'sub FPC_EXCEPTION_INEXACT () {0x1000;}' unless defined(&FPC_EXCEPTION_INEXACT);
	eval 'sub FPC_EXCEPTION_UNDERFLOW () {0x2000;}' unless defined(&FPC_EXCEPTION_UNDERFLOW);
	eval 'sub FPC_EXCEPTION_OVERFLOW () {0x4000;}' unless defined(&FPC_EXCEPTION_OVERFLOW);
	eval 'sub FPC_EXCEPTION_DIV0 () {0x8000;}' unless defined(&FPC_EXCEPTION_DIV0);
	eval 'sub FPC_EXCEPTION_INVALID () {0x10000;}' unless defined(&FPC_EXCEPTION_INVALID);
	eval 'sub FPC_EXCEPTION_UNIMPL () {0x20000;}' unless defined(&FPC_EXCEPTION_UNIMPL);
	eval 'sub FPC_COND_BIT () {0x800000;}' unless defined(&FPC_COND_BIT);
	eval 'sub FPC_FLUSH_BIT () {0x1000000;}' unless defined(&FPC_FLUSH_BIT);
	eval 'sub FPC_MBZ_BITS () {0xfe7c0000;}' unless defined(&FPC_MBZ_BITS);
	eval 'sub OPCODE_SHIFT () {26;}' unless defined(&OPCODE_SHIFT);
	eval 'sub OPCODE_C1 () {0x11;}' unless defined(&OPCODE_C1);
	eval 'sub VMTLB_PF_NUM () {0x3fffffc0;}' unless defined(&VMTLB_PF_NUM);
	eval 'sub VMTLB_ATTR_MASK () {0x38;}' unless defined(&VMTLB_ATTR_MASK);
	eval 'sub VMTLB_MOD_BIT () {0x4;}' unless defined(&VMTLB_MOD_BIT);
	eval 'sub VMTLB_VALID_BIT () {0x2;}' unless defined(&VMTLB_VALID_BIT);
	eval 'sub VMTLB_GLOBAL_BIT () {0x1;}' unless defined(&VMTLB_GLOBAL_BIT);
	eval 'sub VMTLB_PHYS_PAGE_SHIFT () {6;}' unless defined(&VMTLB_PHYS_PAGE_SHIFT);
	eval 'sub VMTLB_VIRT_PAGE_NUM () {0xffffe000;}' unless defined(&VMTLB_VIRT_PAGE_NUM);
	eval 'sub VMTLB_PID () {0xff;}' unless defined(&VMTLB_PID);
	eval 'sub VMTLB_PID_SHIFT () {0;}' unless defined(&VMTLB_PID_SHIFT);
	eval 'sub VMTLB_VIRT_PAGE_SHIFT () {12;}' unless defined(&VMTLB_VIRT_PAGE_SHIFT);
	eval 'sub VMNUM_PIDS () {256;}' unless defined(&VMNUM_PIDS);
	eval 'sub VMTLB_NOT_FOUND () {0;}' unless defined(&VMTLB_NOT_FOUND);
	eval 'sub VMTLB_FOUND () {1;}' unless defined(&VMTLB_FOUND);
	eval 'sub VMTLB_FOUND_WITH_PATCH () {2;}' unless defined(&VMTLB_FOUND_WITH_PATCH);
	eval 'sub VMTLB_PROBE_ERROR () {3;}' unless defined(&VMTLB_PROBE_ERROR);
	eval 'sub COPY_SIGCODE () {1;}' unless defined(&COPY_SIGCODE);
	eval 'sub cpu_wait {
	    my($p) = @_;
    	    eval q();
	}' unless defined(&cpu_wait);
	unless(defined(&_LOCORE)) {
	    require 'machine/frame.ph';
	    eval 'sub clockframe () { &trap_frame;}' unless defined(&clockframe);
	    eval 'sub CLKF_USERMODE {
	        my($framep) = @_;
    		eval q((($framep)-> &sr &  &SR_KSU_USER));
	    }' unless defined(&CLKF_USERMODE);
	    eval 'sub CLKF_PC {
	        my($framep) = @_;
    		eval q((($framep)-> &pc));
	    }' unless defined(&CLKF_PC);
	    eval 'sub CLKF_INTR {
	        my($framep) = @_;
    		eval q(( &int_nest_cntr > 0));
	    }' unless defined(&CLKF_INTR);
	    eval 'sub PROC_PC {
	        my($p) = @_;
    		eval q((($p)-> ($p_md->{md_regs}->{pc})));
	    }' unless defined(&PROC_PC);
	    eval 'sub need_resched {
	        my($info) = @_;
    		eval q({  &want_resched = 1;  &aston(); });
	    }' unless defined(&need_resched);
	    eval 'sub need_proftick {
	        my($p) = @_;
    		eval q({ ($p)-> &p_flag |=  &P_OWEUPC;  &aston(); });
	    }' unless defined(&need_proftick);
	    eval 'sub signotify {
	        my($p) = @_;
    		eval q( &aston());
	    }' unless defined(&signotify);
	    eval 'sub aston () {
	        eval q(( &astpending = 1));
	    }' unless defined(&aston);
	}
    }
    eval 'sub CPU_ALLOWAPERTURE () {1;}' unless defined(&CPU_ALLOWAPERTURE);
    eval 'sub CPU_MAXID () {2;}' unless defined(&CPU_MAXID);
    eval 'sub CTL_MACHDEP_NAMES () {{ { 0, 0}, { "allowaperture",  &CTLTYPE_INT }, };}' unless defined(&CTL_MACHDEP_NAMES);
    eval 'sub MIPS_R2000 () {0x1;}' unless defined(&MIPS_R2000);
    eval 'sub MIPS_R3000 () {0x2;}' unless defined(&MIPS_R3000);
    eval 'sub MIPS_R6000 () {0x3;}' unless defined(&MIPS_R6000);
    eval 'sub MIPS_R4000 () {0x4;}' unless defined(&MIPS_R4000);
    eval 'sub MIPS_R3LSI () {0x5;}' unless defined(&MIPS_R3LSI);
    eval 'sub MIPS_R6000A () {0x6;}' unless defined(&MIPS_R6000A);
    eval 'sub MIPS_R3IDT () {0x7;}' unless defined(&MIPS_R3IDT);
    eval 'sub MIPS_R10000 () {0x9;}' unless defined(&MIPS_R10000);
    eval 'sub MIPS_R4200 () {0xa;}' unless defined(&MIPS_R4200);
    eval 'sub MIPS_R4300 () {0xb;}' unless defined(&MIPS_R4300);
    eval 'sub MIPS_R4100 () {0xc;}' unless defined(&MIPS_R4100);
    eval 'sub MIPS_R12000 () {0xe;}' unless defined(&MIPS_R12000);
    eval 'sub MIPS_R14000 () {0xf;}' unless defined(&MIPS_R14000);
    eval 'sub MIPS_R8000 () {0x10;}' unless defined(&MIPS_R8000);
    eval 'sub MIPS_R4600 () {0x20;}' unless defined(&MIPS_R4600);
    eval 'sub MIPS_R4700 () {0x21;}' unless defined(&MIPS_R4700);
    eval 'sub MIPS_R3TOSH () {0x22;}' unless defined(&MIPS_R3TOSH);
    eval 'sub MIPS_R5000 () {0x23;}' unless defined(&MIPS_R5000);
    eval 'sub MIPS_RM7000 () {0x27;}' unless defined(&MIPS_RM7000);
    eval 'sub MIPS_RM52X0 () {0x28;}' unless defined(&MIPS_RM52X0);
    eval 'sub MIPS_RM9000 () {0x34;}' unless defined(&MIPS_RM9000);
    eval 'sub MIPS_VR5400 () {0x54;}' unless defined(&MIPS_VR5400);
    eval 'sub MIPS_SOFT () {0x;}' unless defined(&MIPS_SOFT);
    if(defined( &_KERNEL)  && !defined( &_LOCORE)) {
	eval 'sub Mips_SyncCache () {
	    eval q((*( ($sys_config->{_SyncCache})))());
	}' unless defined(&Mips_SyncCache);
	eval 'sub Mips_InvalidateICache {
	    my($a, $l) = @_;
    	    eval q((*( ($sys_config->{_InvalidateICache})))(($a), ($l)));
	}' unless defined(&Mips_InvalidateICache);
	eval 'sub Mips_InvalidateICachePage {
	    my($a) = @_;
    	    eval q((*( ($sys_config->{_InvalidateICachePage})))(($a)));
	}' unless defined(&Mips_InvalidateICachePage);
	eval 'sub Mips_SyncDCachePage {
	    my($a) = @_;
    	    eval q((*( ($sys_config->{_SyncDCachePage})))(($a)));
	}' unless defined(&Mips_SyncDCachePage);
	eval 'sub Mips_HitSyncDCache {
	    my($a, $l) = @_;
    	    eval q((*( ($sys_config->{_HitSyncDCache})))(($a), ($l)));
	}' unless defined(&Mips_HitSyncDCache);
	eval 'sub Mips_IOSyncDCache {
	    my($a, $l, $h) = @_;
    	    eval q((*( ($sys_config->{_IOSyncDCache})))(($a), ($l), ($h)));
	}' unless defined(&Mips_IOSyncDCache);
	eval 'sub Mips_HitInvalidateDCache {
	    my($a, $l) = @_;
    	    eval q((*( ($sys_config->{_HitInvalidateDCache})))(($a), ($l)));
	}' unless defined(&Mips_HitInvalidateDCache);
    }
}
1;
