require '_h2ph_pre.ph';

no warnings 'redefine';

unless(defined(&__IF_SANTE1_H)) {
    eval 'sub __IF_SANTE1_H () {1;}' unless defined(&__IF_SANTE1_H);
    if(defined(&SDLA_TE1)) {
	eval 'sub EXTERN () {1;}' unless defined(&EXTERN);
    } else {
	eval 'sub EXTERN () { &extern;}' unless defined(&EXTERN);
    }
    require 'dev/pci/if_san_front_end.ph';
    eval 'sub REG_GLOBAL_CFG () {0x;}' unless defined(&REG_GLOBAL_CFG);
    eval 'sub BIT_GLOBAL_PIO_OE () {0x80;}' unless defined(&BIT_GLOBAL_PIO_OE);
    eval 'sub BIT_GLOBAL_PIO () {0x40;}' unless defined(&BIT_GLOBAL_PIO);
    eval 'sub BIT_GLOBAL_TRKEN () {0x4;}' unless defined(&BIT_GLOBAL_TRKEN);
    eval 'sub BIT_GLOBAL_E1 () {0x1;}' unless defined(&BIT_GLOBAL_E1);
    eval 'sub REG_RLPS_ALOS_DET_PER_0 () {0x1;}' unless defined(&REG_RLPS_ALOS_DET_PER_0);
    eval 'sub REG_RECEIVE_OPT () {0x2;}' unless defined(&REG_RECEIVE_OPT);
    eval 'sub BIT_RECEIVE_OPT_UNF () {0x40;}' unless defined(&BIT_RECEIVE_OPT_UNF);
    eval 'sub REG_TX_TIMING_OPT () {0x6;}' unless defined(&REG_TX_TIMING_OPT);
    eval 'sub BIT_TX_PLLREF1 () {0x8;}' unless defined(&BIT_TX_PLLREF1);
    eval 'sub BIT_TX_PLLREF0 () {0x4;}' unless defined(&BIT_TX_PLLREF0);
    eval 'sub BIT_TX_TXELSTBYP () {0x1;}' unless defined(&BIT_TX_TXELSTBYP);
    eval 'sub REG_MASTER_DIAG () {0xa;}' unless defined(&REG_MASTER_DIAG);
    eval 'sub BIT_MASTER_DIAG_PAYLB () {0x20;}' unless defined(&BIT_MASTER_DIAG_PAYLB);
    eval 'sub BIT_MASTER_DIAG_LINELB () {0x10;}' unless defined(&BIT_MASTER_DIAG_LINELB);
    eval 'sub BIT_MASTER_DIAG_DDLB () {0x4;}' unless defined(&BIT_MASTER_DIAG_DDLB);
    eval 'sub REG_RESET () {0xe;}' unless defined(&REG_RESET);
    eval 'sub BIT_RESET () {0x1;}' unless defined(&BIT_RESET);
    eval 'sub REG_PRGD_CTRL () {0xf;}' unless defined(&REG_PRGD_CTRL);
    eval 'sub BIT_PRGD_CTRL_HDLC3 () {0x80;}' unless defined(&BIT_PRGD_CTRL_HDLC3);
    eval 'sub BIT_PRGD_CTRL_HDLC2 () {0x40;}' unless defined(&BIT_PRGD_CTRL_HDLC2);
    eval 'sub BIT_PRGD_CTRL_HDLC1 () {0x20;}' unless defined(&BIT_PRGD_CTRL_HDLC1);
    eval 'sub BIT_PRGD_CTRL_Nx56k_GEN () {0x10;}' unless defined(&BIT_PRGD_CTRL_Nx56k_GEN);
    eval 'sub BIT_PRGD_CTRL_Nx56k_DET () {0x8;}' unless defined(&BIT_PRGD_CTRL_Nx56k_DET);
    eval 'sub BIT_PRGD_CTRL_RXPATGEN () {0x4;}' unless defined(&BIT_PRGD_CTRL_RXPATGEN);
    eval 'sub BIT_PRGD_CTRL_UNF_GEN () {0x2;}' unless defined(&BIT_PRGD_CTRL_UNF_GEN);
    eval 'sub BIT_PRGD_CTRL_UNF_DET () {0x1;}' unless defined(&BIT_PRGD_CTRL_UNF_DET);
    eval 'sub REG_CDRC_CFG () {0x10;}' unless defined(&REG_CDRC_CFG);
    eval 'sub BIT_CDRC_CFG_AMI () {0x80;}' unless defined(&BIT_CDRC_CFG_AMI);
    eval 'sub BIT_CDRC_CFG_LOS1 () {0x40;}' unless defined(&BIT_CDRC_CFG_LOS1);
    eval 'sub BIT_CDRC_CFG_LOS0 () {0x20;}' unless defined(&BIT_CDRC_CFG_LOS0);
    eval 'sub REG_CDRC_INT_STATUS () {0x12;}' unless defined(&REG_CDRC_INT_STATUS);
    eval 'sub BIT_CDRC_INT_STATUS_LCVI () {0x80;}' unless defined(&BIT_CDRC_INT_STATUS_LCVI);
    eval 'sub BIT_CDRC_INT_STATUS_LOSI () {0x40;}' unless defined(&BIT_CDRC_INT_STATUS_LOSI);
    eval 'sub BIT_CDRC_INT_STATUS_LCSDI () {0x20;}' unless defined(&BIT_CDRC_INT_STATUS_LCSDI);
    eval 'sub BIT_CDRC_INT_STATUS_ZNDI () {0x10;}' unless defined(&BIT_CDRC_INT_STATUS_ZNDI);
    eval 'sub BIT_CDRC_INT_STATUS_LOSV () {0x1;}' unless defined(&BIT_CDRC_INT_STATUS_LOSV);
    eval 'sub REG_ALTLOS_STATUS () {0x13;}' unless defined(&REG_ALTLOS_STATUS);
    eval 'sub BIT_ALTLOS_STATUS_ALTLOSE () {0x80;}' unless defined(&BIT_ALTLOS_STATUS_ALTLOSE);
    eval 'sub BIT_ALTLOS_STATUS_ALTLOSI () {0x40;}' unless defined(&BIT_ALTLOS_STATUS_ALTLOSI);
    eval 'sub BIT_ALTLOS_STATUS_ALTLOS () {0x1;}' unless defined(&BIT_ALTLOS_STATUS_ALTLOS);
    eval 'sub REG_RJAT_CFG () {0x17;}' unless defined(&REG_RJAT_CFG);
    eval 'sub BIT_RJAT_CENT () {0x10;}' unless defined(&BIT_RJAT_CENT);
    eval 'sub REG_TJAT_CFG () {0x1b;}' unless defined(&REG_TJAT_CFG);
    eval 'sub BIT_TJAT_CENT () {0x10;}' unless defined(&BIT_TJAT_CENT);
    eval 'sub REG_RX_ELST_CFG () {0x1c;}' unless defined(&REG_RX_ELST_CFG);
    eval 'sub MASK_RX_ELST_CFG () {0x3;}' unless defined(&MASK_RX_ELST_CFG);
    eval 'sub BIT_RX_ELST_IR () {0x2;}' unless defined(&BIT_RX_ELST_IR);
    eval 'sub BIT_RX_ELST_OR () {0x1;}' unless defined(&BIT_RX_ELST_OR);
    eval 'sub REG_TX_ELST_CFG () {0x20;}' unless defined(&REG_TX_ELST_CFG);
    eval 'sub MASK_TX_ELST_CFG () {0x3;}' unless defined(&MASK_TX_ELST_CFG);
    eval 'sub BIT_TX_ELST_IR () {0x2;}' unless defined(&BIT_TX_ELST_IR);
    eval 'sub BIT_TX_ELST_OR () {0x1;}' unless defined(&BIT_TX_ELST_OR);
    eval 'sub REG_BRIF_CFG () {0x30;}' unless defined(&REG_BRIF_CFG);
    eval 'sub BIT_BRIF_NXDS0_1 () {0x80;}' unless defined(&BIT_BRIF_NXDS0_1);
    eval 'sub BIT_BRIF_NXDS0_0 () {0x40;}' unless defined(&BIT_BRIF_NXDS0_0);
    eval 'sub BIT_BRIF_CMODE () {0x20;}' unless defined(&BIT_BRIF_CMODE);
    eval 'sub BIT_BRIF_RATE0 () {0x1;}' unless defined(&BIT_BRIF_RATE0);
    eval 'sub REG_BRIF_FR_PULSE_CFG () {0x31;}' unless defined(&REG_BRIF_FR_PULSE_CFG);
    eval 'sub BIT_BRIF_FPMODE () {0x20;}' unless defined(&BIT_BRIF_FPMODE);
    eval 'sub BIT_BRIF_ROHM () {0x8;}' unless defined(&BIT_BRIF_ROHM);
    eval 'sub REG_BRIF_DATA_CFG () {0x32;}' unless defined(&REG_BRIF_DATA_CFG);
    eval 'sub BIT_BRIF_DATA_TRI_0 () {0x1;}' unless defined(&BIT_BRIF_DATA_TRI_0);
    eval 'sub REG_BTIF_CFG () {0x40;}' unless defined(&REG_BTIF_CFG);
    eval 'sub BIT_BTIF_NXDS0_1 () {0x80;}' unless defined(&BIT_BTIF_NXDS0_1);
    eval 'sub BIT_BTIF_NXDS0_0 () {0x40;}' unless defined(&BIT_BTIF_NXDS0_0);
    eval 'sub BIT_BTIF_CMODE () {0x20;}' unless defined(&BIT_BTIF_CMODE);
    eval 'sub BIT_BTIF_DE () {0x10;}' unless defined(&BIT_BTIF_DE);
    eval 'sub BIT_BTIF_FE () {0x8;}' unless defined(&BIT_BTIF_FE);
    eval 'sub BIT_BTIF_RATE0 () {0x1;}' unless defined(&BIT_BTIF_RATE0);
    eval 'sub REG_BTIF_FR_PULSE_CFG () {0x41;}' unless defined(&REG_BTIF_FR_PULSE_CFG);
    eval 'sub BIT_BTIF_FPMODE () {0x1;}' unless defined(&BIT_BTIF_FPMODE);
    eval 'sub REG_BTIF_CFG_STATUS () {0x42;}' unless defined(&REG_BTIF_CFG_STATUS);
    eval 'sub BIT_BTIF_CFG_STATUS_TPTYP () {0x80;}' unless defined(&BIT_BTIF_CFG_STATUS_TPTYP);
    eval 'sub BIT_BTIF_CFG_STATUS_TPTYE () {0x40;}' unless defined(&BIT_BTIF_CFG_STATUS_TPTYE);
    eval 'sub BIT_BTIF_CFG_STATUS_TDI () {0x20;}' unless defined(&BIT_BTIF_CFG_STATUS_TDI);
    eval 'sub BIT_BTIF_CFG_STATUS_TSIGI () {0x10;}' unless defined(&BIT_BTIF_CFG_STATUS_TSIGI);
    eval 'sub BIT_BTIF_CFG_STATUS_PTY_EXTD () {0x8;}' unless defined(&BIT_BTIF_CFG_STATUS_PTY_EXTD);
    eval 'sub REG_BTIF_BIT_OFF () {0x44;}' unless defined(&REG_BTIF_BIT_OFF);
    eval 'sub BIT_BTIF_BIT_OFF_BOFF_EN () {0x8;}' unless defined(&BIT_BTIF_BIT_OFF_BOFF_EN);
    eval 'sub BIT_BTIF_BIT_OFF_BOFF_2 () {0x4;}' unless defined(&BIT_BTIF_BIT_OFF_BOFF_2);
    eval 'sub BIT_BTIF_BIT_OFF_BOFF_1 () {0x2;}' unless defined(&BIT_BTIF_BIT_OFF_BOFF_1);
    eval 'sub BIT_BTIF_BIT_OFF_BOFF_0 () {0x1;}' unless defined(&BIT_BTIF_BIT_OFF_BOFF_0);
    eval 'sub REG_T1_FRMR_CFG () {0x48;}' unless defined(&REG_T1_FRMR_CFG);
    eval 'sub BIT_T1_FRMR_ESF () {0x20;}' unless defined(&BIT_T1_FRMR_ESF);
    eval 'sub BIT_T1_FRMR_ESFFA () {0x10;}' unless defined(&BIT_T1_FRMR_ESFFA);
    eval 'sub BIT_T1_FRMR_FMS1 () {0x8;}' unless defined(&BIT_T1_FRMR_FMS1);
    eval 'sub BIT_T1_FRMR_FMS0 () {0x4;}' unless defined(&BIT_T1_FRMR_FMS0);
    eval 'sub REG_SIGX_CFG () {0x50;}' unless defined(&REG_SIGX_CFG);
    eval 'sub BIT_SIGX_ESF () {0x4;}' unless defined(&BIT_SIGX_ESF);
    eval 'sub BIT_SIGX_IND () {0x2;}' unless defined(&BIT_SIGX_IND);
    eval 'sub BIT_SIGX_PCCE () {0x1;}' unless defined(&BIT_SIGX_PCCE);
    eval 'sub BIT_SIGX_SIGE () {0x20;}' unless defined(&BIT_SIGX_SIGE);
    eval 'sub BIT_SIGX_COSS () {0x40;}' unless defined(&BIT_SIGX_COSS);
    eval 'sub MASK_SIGX_COSS_30_25 () {0x3f;}' unless defined(&MASK_SIGX_COSS_30_25);
    eval 'sub REG_SIGX_TIMESLOT_IND_STATUS () {0x51;}' unless defined(&REG_SIGX_TIMESLOT_IND_STATUS);
    eval 'sub BIT_SIGX_BUSY () {0x80;}' unless defined(&BIT_SIGX_BUSY);
    eval 'sub REG_SIGX_TIMESLOT_IND_ACCESS () {0x52;}' unless defined(&REG_SIGX_TIMESLOT_IND_ACCESS);
    eval 'sub BIT_SIGX_TS_IND_ACCESS_READ () {0x80;}' unless defined(&BIT_SIGX_TS_IND_ACCESS_READ);
    eval 'sub REG_SIGX_TIMESLOT_IND_DATA_BUFFER () {0x53;}' unless defined(&REG_SIGX_TIMESLOT_IND_DATA_BUFFER);
    eval 'sub REG_SIGX_SIGDATA () {0x20;}' unless defined(&REG_SIGX_SIGDATA);
    eval 'sub BIT_SIGX_SIGDATA_A () {0x8;}' unless defined(&BIT_SIGX_SIGDATA_A);
    eval 'sub BIT_SIGX_SIGDATA_B () {0x4;}' unless defined(&BIT_SIGX_SIGDATA_B);
    eval 'sub BIT_SIGX_SIGDATA_C () {0x2;}' unless defined(&BIT_SIGX_SIGDATA_C);
    eval 'sub BIT_SIGX_SIGDATA_D () {0x1;}' unless defined(&BIT_SIGX_SIGDATA_D);
    eval 'sub REG_SIGX_CHANCFG () {0x40;}' unless defined(&REG_SIGX_CHANCFG);
    eval 'sub BIT_SIGX_CHANCFG_RINV1 () {0x8;}' unless defined(&BIT_SIGX_CHANCFG_RINV1);
    eval 'sub BIT_SIGX_CHANCFG_RINV0 () {0x4;}' unless defined(&BIT_SIGX_CHANCFG_RINV0);
    eval 'sub BIT_SIGX_CHANCFG_RFIX () {0x4;}' unless defined(&BIT_SIGX_CHANCFG_RFIX);
    eval 'sub BIT_SIGX_CHANCFG_RPOL () {0x2;}' unless defined(&BIT_SIGX_CHANCFG_RPOL);
    eval 'sub BIT_SIGX_CHANCFG_RDEBE () {0x1;}' unless defined(&BIT_SIGX_CHANCFG_RDEBE);
    eval 'sub REG_T1_XBAS_CFG () {0x54;}' unless defined(&REG_T1_XBAS_CFG);
    eval 'sub BIT_T1_XBAS_ZCS0 () {0x1;}' unless defined(&BIT_T1_XBAS_ZCS0);
    eval 'sub BIT_T1_XBAS_ZCS1 () {0x2;}' unless defined(&BIT_T1_XBAS_ZCS1);
    eval 'sub BIT_T1_XBAS_B8ZS () {0x20;}' unless defined(&BIT_T1_XBAS_B8ZS);
    eval 'sub BIT_T1_XBAS_ESF () {0x10;}' unless defined(&BIT_T1_XBAS_ESF);
    eval 'sub REG_T1_XBAS_ALARM_TX () {0x55;}' unless defined(&REG_T1_XBAS_ALARM_TX);
    eval 'sub BIT_T1_XBAS_ALARM_TX_XYEL () {0x2;}' unless defined(&BIT_T1_XBAS_ALARM_TX_XYEL);
    eval 'sub BIT_T1_XBAS_ALARM_TX_XAIS () {0x1;}' unless defined(&BIT_T1_XBAS_ALARM_TX_XAIS);
    eval 'sub REG_PMON_BIT_ERROR () {0x59;}' unless defined(&REG_PMON_BIT_ERROR);
    eval 'sub BITS_PMON_BIT_ERROR () {0x7f;}' unless defined(&BITS_PMON_BIT_ERROR);
    eval 'sub REG_PMON_OOF_FEB_LSB_ERROR () {0x5a;}' unless defined(&REG_PMON_OOF_FEB_LSB_ERROR);
    eval 'sub REG_PMON_OOF_FEB_MSB_ERROR () {0x5b;}' unless defined(&REG_PMON_OOF_FEB_MSB_ERROR);
    eval 'sub BITS_PMON_OOF_FEB_MSB_ERROR () {0x3;}' unless defined(&BITS_PMON_OOF_FEB_MSB_ERROR);
    eval 'sub REG_PMON_BIT_CRC_LSB_ERROR () {0x5c;}' unless defined(&REG_PMON_BIT_CRC_LSB_ERROR);
    eval 'sub REG_PMON_BIT_CRC_MSB_ERROR () {0x5d;}' unless defined(&REG_PMON_BIT_CRC_MSB_ERROR);
    eval 'sub BITS_PMON_BIT_CRC_MSB_ERROR () {0x3;}' unless defined(&BITS_PMON_BIT_CRC_MSB_ERROR);
    eval 'sub REG_PMON_LCV_LSB_COUNT () {0x5e;}' unless defined(&REG_PMON_LCV_LSB_COUNT);
    eval 'sub REG_PMON_LCV_MSB_COUNT () {0x5f;}' unless defined(&REG_PMON_LCV_MSB_COUNT);
    eval 'sub BITS_PMON_LCV_MSB_COUNT () {0x1f;}' unless defined(&BITS_PMON_LCV_MSB_COUNT);
    eval 'sub REG_T1_ALMI_CFG () {0x60;}' unless defined(&REG_T1_ALMI_CFG);
    eval 'sub BIT_T1_ALMI_CFG_ESF () {0x10;}' unless defined(&BIT_T1_ALMI_CFG_ESF);
    eval 'sub BIT_T1_ALMI_CFG_FMS1 () {0x8;}' unless defined(&BIT_T1_ALMI_CFG_FMS1);
    eval 'sub BIT_T1_ALMI_CFG_FMS0 () {0x4;}' unless defined(&BIT_T1_ALMI_CFG_FMS0);
    eval 'sub REG_T1_ALMI_DET_STATUS () {0x63;}' unless defined(&REG_T1_ALMI_DET_STATUS);
    eval 'sub BIT_T1_ALMI_DET_STATUS_REDD () {0x4;}' unless defined(&BIT_T1_ALMI_DET_STATUS_REDD);
    eval 'sub BIT_T1_ALMI_DET_STATUS_YELD () {0x2;}' unless defined(&BIT_T1_ALMI_DET_STATUS_YELD);
    eval 'sub BIT_T1_ALMI_DET_STATUS_AISD () {0x1;}' unless defined(&BIT_T1_ALMI_DET_STATUS_AISD);
    eval 'sub REG_T1_XBOC_CODE () {0x67;}' unless defined(&REG_T1_XBOC_CODE);
    eval 'sub MASK_T1_XBOC_CODE () {0x3f;}' unless defined(&MASK_T1_XBOC_CODE);
    eval 'sub REG_T1_RBOC_ENABLE () {0x6a;}' unless defined(&REG_T1_RBOC_ENABLE);
    eval 'sub BIT_T1_RBOC_ENABLE_IDLE () {0x4;}' unless defined(&BIT_T1_RBOC_ENABLE_IDLE);
    eval 'sub BIT_T1_RBOC_ENABLE_AVC () {0x2;}' unless defined(&BIT_T1_RBOC_ENABLE_AVC);
    eval 'sub BIT_T1_RBOC_ENABLE_BOCE () {0x1;}' unless defined(&BIT_T1_RBOC_ENABLE_BOCE);
    eval 'sub REG_T1_RBOC_CODE_STATUS () {0x6b;}' unless defined(&REG_T1_RBOC_CODE_STATUS);
    eval 'sub BIT_T1_RBOC_CODE_STATUS_IDLEI () {0x80;}' unless defined(&BIT_T1_RBOC_CODE_STATUS_IDLEI);
    eval 'sub BIT_T1_RBOC_CODE_STATUS_BOCI () {0x40;}' unless defined(&BIT_T1_RBOC_CODE_STATUS_BOCI);
    eval 'sub MASK_T1_RBOC_CODE_STATUS () {0x3f;}' unless defined(&MASK_T1_RBOC_CODE_STATUS);
    eval 'sub REG_TPSC_CFG () {0x6c;}' unless defined(&REG_TPSC_CFG);
    eval 'sub MASK_TPSC_CFG () {0x3;}' unless defined(&MASK_TPSC_CFG);
    eval 'sub BIT_TPSC_IND () {0x2;}' unless defined(&BIT_TPSC_IND);
    eval 'sub BIT_TPSC_PCCE () {0x1;}' unless defined(&BIT_TPSC_PCCE);
    eval 'sub REG_TPSC_MICRO_ACCESS_STATUS () {0x6d;}' unless defined(&REG_TPSC_MICRO_ACCESS_STATUS);
    eval 'sub BIT_TPSC_BUSY () {0x80;}' unless defined(&BIT_TPSC_BUSY);
    eval 'sub REG_TPSC_CHANNEL_INDIRECT_ADDRESS_CONTROL () {0x6e;}' unless defined(&REG_TPSC_CHANNEL_INDIRECT_ADDRESS_CONTROL);
    eval 'sub REG_TPSC_CHANNEL_INDIRECT_DATA_BUFFER () {0x6f;}' unless defined(&REG_TPSC_CHANNEL_INDIRECT_DATA_BUFFER);
    eval 'sub REG_TPSC_DATA_CTRL_BYTE () {0x20;}' unless defined(&REG_TPSC_DATA_CTRL_BYTE);
    eval 'sub MASK_TPSC_DATA_CTRL_BYTE () {0xfc;}' unless defined(&MASK_TPSC_DATA_CTRL_BYTE);
    eval 'sub BIT_TPSC_DATA_CTRL_BYTE_INVERT () {0x80;}' unless defined(&BIT_TPSC_DATA_CTRL_BYTE_INVERT);
    eval 'sub BIT_TPSC_DATA_CTRL_BYTE_IDLE_DS0 () {0x40;}' unless defined(&BIT_TPSC_DATA_CTRL_BYTE_IDLE_DS0);
    eval 'sub BIT_TPSC_DATA_CTRL_BYTE_SIGNINV () {0x10;}' unless defined(&BIT_TPSC_DATA_CTRL_BYTE_SIGNINV);
    eval 'sub BIT_TPSC_DATA_CTRL_BYTE_LOOP () {0x4;}' unless defined(&BIT_TPSC_DATA_CTRL_BYTE_LOOP);
    eval 'sub BIT_TPSC_DATA_CTRL_BYTE_ZCS0 () {0x2;}' unless defined(&BIT_TPSC_DATA_CTRL_BYTE_ZCS0);
    eval 'sub BIT_TPSC_DATA_CTRL_BYTE_ZCS1 () {0x1;}' unless defined(&BIT_TPSC_DATA_CTRL_BYTE_ZCS1);
    eval 'sub REG_TPSC_IDLE_CODE_BYTE () {0x40;}' unless defined(&REG_TPSC_IDLE_CODE_BYTE);
    eval 'sub REG_TPSC_SIGNALING_BYTE () {0x60;}' unless defined(&REG_TPSC_SIGNALING_BYTE);
    eval 'sub REG_TPSC_E1_CTRL_BYTE () {0x60;}' unless defined(&REG_TPSC_E1_CTRL_BYTE);
    eval 'sub BIT_TPSC_E1_CTRL_BYTE_SUBS () {0x80;}' unless defined(&BIT_TPSC_E1_CTRL_BYTE_SUBS);
    eval 'sub BIT_TPSC_E1_CTRL_BYTE_DS0 () {0x40;}' unless defined(&BIT_TPSC_E1_CTRL_BYTE_DS0);
    eval 'sub BIT_TPSC_E1_CTRL_BYTE_DS1 () {0x20;}' unless defined(&BIT_TPSC_E1_CTRL_BYTE_DS1);
    eval 'sub BIT_TPSC_E1_CTRL_BYTE_A () {0x8;}' unless defined(&BIT_TPSC_E1_CTRL_BYTE_A);
    eval 'sub BIT_TPSC_E1_CTRL_BYTE_B () {0x4;}' unless defined(&BIT_TPSC_E1_CTRL_BYTE_B);
    eval 'sub BIT_TPSC_E1_CTRL_BYTE_C () {0x2;}' unless defined(&BIT_TPSC_E1_CTRL_BYTE_C);
    eval 'sub BIT_TPSC_E1_CTRL_BYTE_D () {0x1;}' unless defined(&BIT_TPSC_E1_CTRL_BYTE_D);
    eval 'sub BIT_TPSC_SIGNALING_BYTE_SIGC_0 () {0x80;}' unless defined(&BIT_TPSC_SIGNALING_BYTE_SIGC_0);
    eval 'sub BIT_TPSC_SIGNALING_BYTE_SIGC_1 () {0x40;}' unless defined(&BIT_TPSC_SIGNALING_BYTE_SIGC_1);
    eval 'sub BIT_TPSC_SIGNALING_BYTE_DS1 () {0x20;}' unless defined(&BIT_TPSC_SIGNALING_BYTE_DS1);
    eval 'sub BIT_TPSC_SIGNALING_BYTE_A () {0x8;}' unless defined(&BIT_TPSC_SIGNALING_BYTE_A);
    eval 'sub BIT_TPSC_SIGNALING_BYTE_B () {0x4;}' unless defined(&BIT_TPSC_SIGNALING_BYTE_B);
    eval 'sub BIT_TPSC_SIGNALING_BYTE_C () {0x2;}' unless defined(&BIT_TPSC_SIGNALING_BYTE_C);
    eval 'sub BIT_TPSC_SIGNALING_BYTE_D () {0x1;}' unless defined(&BIT_TPSC_SIGNALING_BYTE_D);
    eval 'sub REG_RPSC_CFG () {0x70;}' unless defined(&REG_RPSC_CFG);
    eval 'sub MASK_RPSC_CFG () {0x3;}' unless defined(&MASK_RPSC_CFG);
    eval 'sub BIT_RPSC_IND () {0x2;}' unless defined(&BIT_RPSC_IND);
    eval 'sub BIT_RPSC_PCCE () {0x1;}' unless defined(&BIT_RPSC_PCCE);
    eval 'sub REG_RPSC_MICRO_ACCESS_STATUS () {0x71;}' unless defined(&REG_RPSC_MICRO_ACCESS_STATUS);
    eval 'sub BIT_RPSC_BUSY () {0x80;}' unless defined(&BIT_RPSC_BUSY);
    eval 'sub REG_RPSC_CHANNEL_INDIRECT_ADDRESS_CONTROL () {0x72;}' unless defined(&REG_RPSC_CHANNEL_INDIRECT_ADDRESS_CONTROL);
    eval 'sub REG_RPSC_CHANNEL_INDIRECT_DATA_BUFFER () {0x73;}' unless defined(&REG_RPSC_CHANNEL_INDIRECT_DATA_BUFFER);
    eval 'sub REG_RPSC_DATA_CTRL_BYTE () {0x20;}' unless defined(&REG_RPSC_DATA_CTRL_BYTE);
    eval 'sub MASK_RPSC_DATA_CTRL_BYTE () {0xfc;}' unless defined(&MASK_RPSC_DATA_CTRL_BYTE);
    eval 'sub BIT_RPSC_DATA_CTRL_BYTE_DTRKC () {0x40;}' unless defined(&BIT_RPSC_DATA_CTRL_BYTE_DTRKC);
    eval 'sub BIT_RPSC_DATA_CTRL_BYTE_SIGNINV () {0x4;}' unless defined(&BIT_RPSC_DATA_CTRL_BYTE_SIGNINV);
    eval 'sub REG_RPSC_DATA_COND_BYTE () {0x40;}' unless defined(&REG_RPSC_DATA_COND_BYTE);
    eval 'sub REG_RPSC_SIGNALING_BYTE () {0x60;}' unless defined(&REG_RPSC_SIGNALING_BYTE);
    eval 'sub BIT_RPSC_SIGNALING_BYTE_A () {0x8;}' unless defined(&BIT_RPSC_SIGNALING_BYTE_A);
    eval 'sub BIT_RPSC_SIGNALING_BYTE_B () {0x4;}' unless defined(&BIT_RPSC_SIGNALING_BYTE_B);
    eval 'sub BIT_RPSC_SIGNALING_BYTE_C () {0x2;}' unless defined(&BIT_RPSC_SIGNALING_BYTE_C);
    eval 'sub BIT_RPSC_SIGNALING_BYTE_D () {0x1;}' unless defined(&BIT_RPSC_SIGNALING_BYTE_D);
    eval 'sub REG_E1_TRAN_CFG () {0x80;}' unless defined(&REG_E1_TRAN_CFG);
    eval 'sub BIT_E1_TRAN_AMI () {0x80;}' unless defined(&BIT_E1_TRAN_AMI);
    eval 'sub BIT_E1_TRAN_GENCRC () {0x10;}' unless defined(&BIT_E1_TRAN_GENCRC);
    eval 'sub BIT_E1_TRAN_FDIS () {0x8;}' unless defined(&BIT_E1_TRAN_FDIS);
    eval 'sub BIT_E1_TRAN_FEBEDIS () {0x4;}' unless defined(&BIT_E1_TRAN_FEBEDIS);
    eval 'sub BIT_E1_TRAN_INDIS () {0x2;}' unless defined(&BIT_E1_TRAN_INDIS);
    eval 'sub BIT_E1_TRAN_XDIS () {0x1;}' unless defined(&BIT_E1_TRAN_XDIS);
    eval 'sub REG_E1_FRMR_CFG () {0x90;}' unless defined(&REG_E1_FRMR_CFG);
    eval 'sub BIT_E1_FRMR_CRCEN () {0x80;}' unless defined(&BIT_E1_FRMR_CRCEN);
    eval 'sub BIT_E1_FRMR_CASDIS () {0x40;}' unless defined(&BIT_E1_FRMR_CASDIS);
    eval 'sub BIT_E1_FRMR_REFCRCEN () {0x2;}' unless defined(&BIT_E1_FRMR_REFCRCEN);
    eval 'sub REG_E1_FRMR_MAINT_OPT () {0x91;}' unless defined(&REG_E1_FRMR_MAINT_OPT);
    eval 'sub BIT_E1_FRMR_MAINT_OPT_AISC () {0x2;}' unless defined(&BIT_E1_FRMR_MAINT_OPT_AISC);
    eval 'sub REG_E1_FRMR_FR_STATUS () {0x96;}' unless defined(&REG_E1_FRMR_FR_STATUS);
    eval 'sub BIT_E1_FRMR_FR_STATUS_C2NCIWV () {0x80;}' unless defined(&BIT_E1_FRMR_FR_STATUS_C2NCIWV);
    eval 'sub BIT_E1_FRMR_FR_STATUS_OOFV () {0x40;}' unless defined(&BIT_E1_FRMR_FR_STATUS_OOFV);
    eval 'sub BIT_E1_FRMR_FR_STATUS_OOSMFV () {0x20;}' unless defined(&BIT_E1_FRMR_FR_STATUS_OOSMFV);
    eval 'sub BIT_E1_FRMR_FR_STATUS_OOCMFV () {0x10;}' unless defined(&BIT_E1_FRMR_FR_STATUS_OOCMFV);
    eval 'sub BIT_E1_FRMR_FR_STATUS_OOOFV () {0x8;}' unless defined(&BIT_E1_FRMR_FR_STATUS_OOOFV);
    eval 'sub BIT_E1_FRMR_FR_STATUS_RAICCRCV () {0x4;}' unless defined(&BIT_E1_FRMR_FR_STATUS_RAICCRCV);
    eval 'sub BIT_E1_FRMR_FR_STATUS_CFEBEV () {0x2;}' unless defined(&BIT_E1_FRMR_FR_STATUS_CFEBEV);
    eval 'sub BIT_E1_FRMR_FR_STATUS_V52LINKV () {0x1;}' unless defined(&BIT_E1_FRMR_FR_STATUS_V52LINKV);
    eval 'sub REG_E1_FRMR_MAINT_STATUS () {0x97;}' unless defined(&REG_E1_FRMR_MAINT_STATUS);
    eval 'sub BIT_E1_FRMR_MAINT_STATUS_RAIV () {0x80;}' unless defined(&BIT_E1_FRMR_MAINT_STATUS_RAIV);
    eval 'sub BIT_E1_FRMR_MAINT_STATUS_RED () {0x8;}' unless defined(&BIT_E1_FRMR_MAINT_STATUS_RED);
    eval 'sub BIT_E1_FRMR_MAINT_STATUS_AIS () {0x4;}' unless defined(&BIT_E1_FRMR_MAINT_STATUS_AIS);
    eval 'sub REG_TDPR_CFG () {0xa8;}' unless defined(&REG_TDPR_CFG);
    eval 'sub BIT_TDPR_CFG_EN () {0x1;}' unless defined(&BIT_TDPR_CFG_EN);
    eval 'sub REG_TDPR_TX_DATA () {0xad;}' unless defined(&REG_TDPR_TX_DATA);
    eval 'sub REG_RDLC_CFG () {0xc0;}' unless defined(&REG_RDLC_CFG);
    eval 'sub BIT_RDLC_CFG_EN () {0x1;}' unless defined(&BIT_RDLC_CFG_EN);
    eval 'sub REG_RDLC_INT_CTRL () {0xc1;}' unless defined(&REG_RDLC_INT_CTRL);
    eval 'sub BIT_RDLC_INT_CTRL_INTE () {0x80;}' unless defined(&BIT_RDLC_INT_CTRL_INTE);
    eval 'sub REG_RDLC_STATUS () {0xc2;}' unless defined(&REG_RDLC_STATUS);
    eval 'sub BIT_RDLC_STATUS_PKIN () {0x10;}' unless defined(&BIT_RDLC_STATUS_PKIN);
    eval 'sub BIT_RDLC_STATUS_INTR () {0x1;}' unless defined(&BIT_RDLC_STATUS_INTR);
    eval 'sub REG_RDLC_DATA () {0xc3;}' unless defined(&REG_RDLC_DATA);
    eval 'sub REG_CSU_CFG () {0xd6;}' unless defined(&REG_CSU_CFG);
    eval 'sub MASK_CSU_CFG () {0xc7;}' unless defined(&MASK_CSU_CFG);
    eval 'sub BIT_CSU_MODE2 () {0x4;}' unless defined(&BIT_CSU_MODE2);
    eval 'sub BIT_CSU_MODE1 () {0x2;}' unless defined(&BIT_CSU_MODE1);
    eval 'sub BIT_CSU_MODE0 () {0x1;}' unless defined(&BIT_CSU_MODE0);
    eval 'sub REG_RLPS_IND_DATA_1 () {0xd8;}' unless defined(&REG_RLPS_IND_DATA_1);
    eval 'sub REG_RLPS_IND_DATA_2 () {0xd9;}' unless defined(&REG_RLPS_IND_DATA_2);
    eval 'sub REG_RLPS_IND_DATA_3 () {0xda;}' unless defined(&REG_RLPS_IND_DATA_3);
    eval 'sub REG_RLPS_IND_DATA_4 () {0xdb;}' unless defined(&REG_RLPS_IND_DATA_4);
    eval 'sub REG_EQ_VREF () {0xdc;}' unless defined(&REG_EQ_VREF);
    eval 'sub REG_RLPS_FUSE_CTRL_STAT () {0xdd;}' unless defined(&REG_RLPS_FUSE_CTRL_STAT);
    eval 'sub REG_XLPG_LINE_CFG () {0xf0;}' unless defined(&REG_XLPG_LINE_CFG);
    eval 'sub REG_PRGD_INT_STATUS_EN () {0xe1;}' unless defined(&REG_PRGD_INT_STATUS_EN);
    eval 'sub BIT_PRGD_INT_STATUS_EN_SYNCE () {0x80;}' unless defined(&BIT_PRGD_INT_STATUS_EN_SYNCE);
    eval 'sub BIT_PRGD_INT_STATUS_EN_BEE () {0x40;}' unless defined(&BIT_PRGD_INT_STATUS_EN_BEE);
    eval 'sub BIT_PRGD_INT_STATUS_EN_XFERE () {0x20;}' unless defined(&BIT_PRGD_INT_STATUS_EN_XFERE);
    eval 'sub BIT_PRGD_INT_STATUS_EN_SYNCV () {0x10;}' unless defined(&BIT_PRGD_INT_STATUS_EN_SYNCV);
    eval 'sub BIT_PRGD_INT_STATUS_EN_SYNCI () {0x8;}' unless defined(&BIT_PRGD_INT_STATUS_EN_SYNCI);
    eval 'sub BIT_PRGD_INT_STATUS_EN_BEI () {0x4;}' unless defined(&BIT_PRGD_INT_STATUS_EN_BEI);
    eval 'sub BIT_PRGD_INT_STATUS_EN_XFERI () {0x2;}' unless defined(&BIT_PRGD_INT_STATUS_EN_XFERI);
    eval 'sub BIT_PRGD_INT_STATUS_EN_OVR () {0x1;}' unless defined(&BIT_PRGD_INT_STATUS_EN_OVR);
    eval 'sub REG_XLPG_WAVEFORM_ADDR () {0xf2;}' unless defined(&REG_XLPG_WAVEFORM_ADDR);
    eval 'sub REG_XLPG_WAVEFORM_DATA () {0xf3;}' unless defined(&REG_XLPG_WAVEFORM_DATA);
    eval 'sub REG_XLPG_TPC () {0xf4;}' unless defined(&REG_XLPG_TPC);
    eval 'sub BIT_XLPG_TPC_0 () {0x1;}' unless defined(&BIT_XLPG_TPC_0);
    eval 'sub REG_XLPG_TNC () {0xf5;}' unless defined(&REG_XLPG_TNC);
    eval 'sub BIT_XLPG_TNC_0 () {0x1;}' unless defined(&BIT_XLPG_TNC_0);
    eval 'sub REG_RLPS_CFG_STATUS () {0xf8;}' unless defined(&REG_RLPS_CFG_STATUS);
    eval 'sub BIT_RLPS_CFG_STATUS_ALOSI () {0x80;}' unless defined(&BIT_RLPS_CFG_STATUS_ALOSI);
    eval 'sub BIT_RLPS_CFG_STATUS_ALOSV () {0x40;}' unless defined(&BIT_RLPS_CFG_STATUS_ALOSV);
    eval 'sub BIT_RLPS_CFG_STATUS_ALOSE () {0x20;}' unless defined(&BIT_RLPS_CFG_STATUS_ALOSE);
    eval 'sub BIT_RLPS_CFG_STATUS_LONGE () {0x1;}' unless defined(&BIT_RLPS_CFG_STATUS_LONGE);
    eval 'sub REG_RLPS_ALOS_DET_CLR_THR () {0xf9;}' unless defined(&REG_RLPS_ALOS_DET_CLR_THR);
    eval 'sub BIT_RLPS_ALOS_CLR_THR_2 () {0x40;}' unless defined(&BIT_RLPS_ALOS_CLR_THR_2);
    eval 'sub BIT_RLPS_ALOS_CLR_THR_1 () {0x20;}' unless defined(&BIT_RLPS_ALOS_CLR_THR_1);
    eval 'sub BIT_RLPS_ALOS_CLR_THR_0 () {0x10;}' unless defined(&BIT_RLPS_ALOS_CLR_THR_0);
    eval 'sub BIT_RLPS_ALOS_DET_THR_2 () {0x4;}' unless defined(&BIT_RLPS_ALOS_DET_THR_2);
    eval 'sub BIT_RLPS_ALOS_DET_THR_1 () {0x2;}' unless defined(&BIT_RLPS_ALOS_DET_THR_1);
    eval 'sub BIT_RLPS_ALOS_DET_THR_0 () {0x1;}' unless defined(&BIT_RLPS_ALOS_DET_THR_0);
    eval 'sub REG_RLPS_ALOS_DET_PER () {0xfa;}' unless defined(&REG_RLPS_ALOS_DET_PER);
    eval 'sub REG_RLPS_ALOS_CLR_PER () {0xfb;}' unless defined(&REG_RLPS_ALOS_CLR_PER);
    eval 'sub BIT_RLPS_ALOS_CLR_PER_0 () {0x1;}' unless defined(&BIT_RLPS_ALOS_CLR_PER_0);
    eval 'sub REG_RLPS_EQ_ADDR () {0xfc;}' unless defined(&REG_RLPS_EQ_ADDR);
    eval 'sub REG_RLPS_EQ_RWB () {0xfd;}' unless defined(&REG_RLPS_EQ_RWB);
    eval 'sub BIT_RLPS_EQ_RWB () {0x80;}' unless defined(&BIT_RLPS_EQ_RWB);
    eval 'sub REG_RLPS_EQ_STATUS () {0xfe;}' unless defined(&REG_RLPS_EQ_STATUS);
    eval 'sub REG_RLPS_EQ_CFG () {0xff;}' unless defined(&REG_RLPS_EQ_CFG);
    eval 'sub MASK_RLPS_EQ_CFG () {0xc7;}' unless defined(&MASK_RLPS_EQ_CFG);
    eval 'sub BIT_RLPS_EQ_RESERVED () {0x8;}' unless defined(&BIT_RLPS_EQ_RESERVED);
    eval 'sub BIT_RLPS_EQ_FREQ_1 () {0x2;}' unless defined(&BIT_RLPS_EQ_FREQ_1);
    eval 'sub BIT_RLPS_EQ_FREQ_0 () {0x1;}' unless defined(&BIT_RLPS_EQ_FREQ_0);
    eval 'sub REG_INT_SRC_1 () {0x7;}' unless defined(&REG_INT_SRC_1);
    eval 'sub BITS_TX_INT_SRC_1 () {0xc;}' unless defined(&BITS_TX_INT_SRC_1);
    eval 'sub BITS_RX_INT_SRC_1 () {0xf3;}' unless defined(&BITS_RX_INT_SRC_1);
    eval 'sub BIT_INT_SRC_1_PMON () {0x80;}' unless defined(&BIT_INT_SRC_1_PMON);
    eval 'sub BIT_INT_SRC_1_PRGD () {0x40;}' unless defined(&BIT_INT_SRC_1_PRGD);
    eval 'sub BIT_INT_SRC_1_FRMR () {0x20;}' unless defined(&BIT_INT_SRC_1_FRMR);
    eval 'sub BIT_INT_SRC_1_SIGX () {0x10;}' unless defined(&BIT_INT_SRC_1_SIGX);
    eval 'sub BIT_INT_SRC_1_APRM () {0x8;}' unless defined(&BIT_INT_SRC_1_APRM);
    eval 'sub BIT_INT_SRC_1_TJAT () {0x4;}' unless defined(&BIT_INT_SRC_1_TJAT);
    eval 'sub BIT_INT_SRC_1_RJAT () {0x2;}' unless defined(&BIT_INT_SRC_1_RJAT);
    eval 'sub BIT_INT_SRC_1_CDRC () {0x1;}' unless defined(&BIT_INT_SRC_1_CDRC);
    eval 'sub REG_INT_SRC_2 () {0x8;}' unless defined(&REG_INT_SRC_2);
    eval 'sub BITS_TX_INT_SRC_2 () {0xf;}' unless defined(&BITS_TX_INT_SRC_2);
    eval 'sub BITS_RX_INT_SRC_2 () {0xf0;}' unless defined(&BITS_RX_INT_SRC_2);
    eval 'sub BIT_INT_SRC_2_RX_ELST () {0x80;}' unless defined(&BIT_INT_SRC_2_RX_ELST);
    eval 'sub BIT_INT_SRC_2_RDLC_3 () {0x40;}' unless defined(&BIT_INT_SRC_2_RDLC_3);
    eval 'sub BIT_INT_SRC_2_RDLC_2 () {0x20;}' unless defined(&BIT_INT_SRC_2_RDLC_2);
    eval 'sub BIT_INT_SRC_2_RDLC_1 () {0x10;}' unless defined(&BIT_INT_SRC_2_RDLC_1);
    eval 'sub BIT_INT_SRC_2_TX_ELST () {0x8;}' unless defined(&BIT_INT_SRC_2_TX_ELST);
    eval 'sub BIT_INT_SRC_2_TDPR_3 () {0x4;}' unless defined(&BIT_INT_SRC_2_TDPR_3);
    eval 'sub BIT_INT_SRC_2_TDPR_2 () {0x2;}' unless defined(&BIT_INT_SRC_2_TDPR_2);
    eval 'sub BIT_INT_SRC_2_TDPR_1 () {0x1;}' unless defined(&BIT_INT_SRC_2_TDPR_1);
    eval 'sub REG_INT_SRC_3 () {0x9;}' unless defined(&REG_INT_SRC_3);
    eval 'sub BITS_TX_INT_SRC_3 () {0x15;}' unless defined(&BITS_TX_INT_SRC_3);
    eval 'sub BITS_RX_INT_SRC_3 () {0xea;}' unless defined(&BITS_RX_INT_SRC_3);
    eval 'sub BIT_INT_SRC_3_IBCD () {0x80;}' unless defined(&BIT_INT_SRC_3_IBCD);
    eval 'sub BIT_INT_SRC_3_PDVD () {0x40;}' unless defined(&BIT_INT_SRC_3_PDVD);
    eval 'sub BIT_INT_SRC_3_RBOC () {0x20;}' unless defined(&BIT_INT_SRC_3_RBOC);
    eval 'sub BIT_INT_SRC_3_XPDE () {0x10;}' unless defined(&BIT_INT_SRC_3_XPDE);
    eval 'sub BIT_INT_SRC_3_ALMI () {0x8;}' unless defined(&BIT_INT_SRC_3_ALMI);
    eval 'sub BIT_INT_SRC_3_TRAN () {0x4;}' unless defined(&BIT_INT_SRC_3_TRAN);
    eval 'sub BIT_INT_SRC_3_RLPS () {0x2;}' unless defined(&BIT_INT_SRC_3_RLPS);
    eval 'sub BIT_INT_SRC_3_BTIF () {0x1;}' unless defined(&BIT_INT_SRC_3_BTIF);
    eval 'sub REG_CDRC_INT_EN () {0x11;}' unless defined(&REG_CDRC_INT_EN);
    eval 'sub BIT_CDRC_INT_EN_LCVE () {0x80;}' unless defined(&BIT_CDRC_INT_EN_LCVE);
    eval 'sub BIT_CDRC_INT_EN_LOSE () {0x40;}' unless defined(&BIT_CDRC_INT_EN_LOSE);
    eval 'sub BIT_CDRC_INT_EN_LCSDE () {0x20;}' unless defined(&BIT_CDRC_INT_EN_LCSDE);
    eval 'sub BIT_CDRC_INT_EN_ZNDE () {0x10;}' unless defined(&BIT_CDRC_INT_EN_ZNDE);
    eval 'sub REG_CDRC_INT_STATUS () {0x12;}' unless defined(&REG_CDRC_INT_STATUS);
    eval 'sub BIT_CDRC_INT_STATUS_LCVI () {0x80;}' unless defined(&BIT_CDRC_INT_STATUS_LCVI);
    eval 'sub BIT_CDRC_INT_STATUS_LOSI () {0x40;}' unless defined(&BIT_CDRC_INT_STATUS_LOSI);
    eval 'sub BIT_CDRC_INT_STATUS_LCSDI () {0x20;}' unless defined(&BIT_CDRC_INT_STATUS_LCSDI);
    eval 'sub BIT_CDRC_INT_STATUS_ZNDI () {0x10;}' unless defined(&BIT_CDRC_INT_STATUS_ZNDI);
    eval 'sub BIT_CDRC_INT_STATUS_LOSV () {0x1;}' unless defined(&BIT_CDRC_INT_STATUS_LOSV);
    eval 'sub REG_RJAT_INT_STATUS () {0x14;}' unless defined(&REG_RJAT_INT_STATUS);
    eval 'sub BIT_RJAT_INT_STATUS_OVRI () {0x2;}' unless defined(&BIT_RJAT_INT_STATUS_OVRI);
    eval 'sub BIT_RJAT_INT_STATUS_UNDI () {0x1;}' unless defined(&BIT_RJAT_INT_STATUS_UNDI);
    eval 'sub REG_TJAT_INT_STATUS () {0x18;}' unless defined(&REG_TJAT_INT_STATUS);
    eval 'sub BIT_TJAT_INT_STATUS_OVRI () {0x2;}' unless defined(&BIT_TJAT_INT_STATUS_OVRI);
    eval 'sub BIT_TJAT_INT_STATUS_UNDI () {0x1;}' unless defined(&BIT_TJAT_INT_STATUS_UNDI);
    eval 'sub REG_RX_ELST_INT_EN_STATUS () {0x1d;}' unless defined(&REG_RX_ELST_INT_EN_STATUS);
    eval 'sub BIT_RX_ELST_INT_EN_STATUS_SLIPE () {0x4;}' unless defined(&BIT_RX_ELST_INT_EN_STATUS_SLIPE);
    eval 'sub BIT_RX_ELST_INT_EN_STATUS_SLIPD () {0x2;}' unless defined(&BIT_RX_ELST_INT_EN_STATUS_SLIPD);
    eval 'sub BIT_RX_ELST_INT_EN_STATUS_SLIPI () {0x1;}' unless defined(&BIT_RX_ELST_INT_EN_STATUS_SLIPI);
    eval 'sub REG_TX_ELST_INT_EN_STATUS () {0x21;}' unless defined(&REG_TX_ELST_INT_EN_STATUS);
    eval 'sub BIT_TX_ELST_INT_EN_STATUS_SLIPE () {0x4;}' unless defined(&BIT_TX_ELST_INT_EN_STATUS_SLIPE);
    eval 'sub BIT_TX_ELST_INT_EN_STATUS_SLIPD () {0x2;}' unless defined(&BIT_TX_ELST_INT_EN_STATUS_SLIPD);
    eval 'sub BIT_TX_ELST_INT_EN_STATUS_SLIPI () {0x1;}' unless defined(&BIT_TX_ELST_INT_EN_STATUS_SLIPI);
    eval 'sub REG_T1_FRMR_INT_EN () {0x49;}' unless defined(&REG_T1_FRMR_INT_EN);
    eval 'sub BIT_T1_FRMR_INT_EN_COFAE () {0x20;}' unless defined(&BIT_T1_FRMR_INT_EN_COFAE);
    eval 'sub BIT_T1_FRMR_INT_EN_FERE () {0x10;}' unless defined(&BIT_T1_FRMR_INT_EN_FERE);
    eval 'sub BIT_T1_FRMR_INT_EN_BEEE () {0x8;}' unless defined(&BIT_T1_FRMR_INT_EN_BEEE);
    eval 'sub BIT_T1_FRMR_INT_EN_SFEE () {0x4;}' unless defined(&BIT_T1_FRMR_INT_EN_SFEE);
    eval 'sub BIT_T1_FRMR_INT_EN_MFPE () {0x2;}' unless defined(&BIT_T1_FRMR_INT_EN_MFPE);
    eval 'sub BIT_T1_FRMR_INT_EN_INFRE () {0x1;}' unless defined(&BIT_T1_FRMR_INT_EN_INFRE);
    eval 'sub REG_T1_FRMR_INT_STATUS () {0x4a;}' unless defined(&REG_T1_FRMR_INT_STATUS);
    eval 'sub BIT_T1_FRMR_INT_STATUS_COFAI () {0x80;}' unless defined(&BIT_T1_FRMR_INT_STATUS_COFAI);
    eval 'sub BIT_T1_FRMR_INT_STATUS_FERI () {0x40;}' unless defined(&BIT_T1_FRMR_INT_STATUS_FERI);
    eval 'sub BIT_T1_FRMR_INT_STATUS_BEEI () {0x20;}' unless defined(&BIT_T1_FRMR_INT_STATUS_BEEI);
    eval 'sub BIT_T1_FRMR_INT_STATUS_SFEI () {0x10;}' unless defined(&BIT_T1_FRMR_INT_STATUS_SFEI);
    eval 'sub BIT_T1_FRMR_INT_STATUS_MFPI () {0x8;}' unless defined(&BIT_T1_FRMR_INT_STATUS_MFPI);
    eval 'sub BIT_T1_FRMR_INT_STATUS_INFRI () {0x4;}' unless defined(&BIT_T1_FRMR_INT_STATUS_INFRI);
    eval 'sub BIT_T1_FRMR_INT_STATUS_MFP () {0x2;}' unless defined(&BIT_T1_FRMR_INT_STATUS_MFP);
    eval 'sub BIT_T1_FRMR_INT_STATUS_INFR () {0x1;}' unless defined(&BIT_T1_FRMR_INT_STATUS_INFR);
    eval 'sub REG_IBCD_CFG () {0x4c;}' unless defined(&REG_IBCD_CFG);
    eval 'sub BIT_IBCD_CFG_DSEL1 () {0x8;}' unless defined(&BIT_IBCD_CFG_DSEL1);
    eval 'sub BIT_IBCD_CFG_DSEL0 () {0x4;}' unless defined(&BIT_IBCD_CFG_DSEL0);
    eval 'sub BIT_IBCD_CFG_ASEL1 () {0x2;}' unless defined(&BIT_IBCD_CFG_ASEL1);
    eval 'sub BIT_IBCD_CFG_ASEL0 () {0x1;}' unless defined(&BIT_IBCD_CFG_ASEL0);
    eval 'sub REG_IBCD_INT_EN_STATUS () {0x4d;}' unless defined(&REG_IBCD_INT_EN_STATUS);
    eval 'sub BIT_IBCD_INT_EN_STATUS_LBACP () {0x80;}' unless defined(&BIT_IBCD_INT_EN_STATUS_LBACP);
    eval 'sub BIT_IBCD_INT_EN_STATUS_LBDCP () {0x40;}' unless defined(&BIT_IBCD_INT_EN_STATUS_LBDCP);
    eval 'sub BIT_IBCD_INT_EN_STATUS_LBAE () {0x20;}' unless defined(&BIT_IBCD_INT_EN_STATUS_LBAE);
    eval 'sub BIT_IBCD_INT_EN_STATUS_LBDE () {0x10;}' unless defined(&BIT_IBCD_INT_EN_STATUS_LBDE);
    eval 'sub BIT_IBCD_INT_EN_STATUS_LBAI () {0x8;}' unless defined(&BIT_IBCD_INT_EN_STATUS_LBAI);
    eval 'sub BIT_IBCD_INT_EN_STATUS_LBDI () {0x4;}' unless defined(&BIT_IBCD_INT_EN_STATUS_LBDI);
    eval 'sub BIT_IBCD_INT_EN_STATUS_LBA () {0x2;}' unless defined(&BIT_IBCD_INT_EN_STATUS_LBA);
    eval 'sub BIT_IBCD_INT_EN_STATUS_LBD () {0x1;}' unless defined(&BIT_IBCD_INT_EN_STATUS_LBD);
    eval 'sub REG_IBCD_ACTIVATE_CODE () {0x4e;}' unless defined(&REG_IBCD_ACTIVATE_CODE);
    eval 'sub BIT_IBCD_ACTIVATE_CODE_ACT7 () {0x80;}' unless defined(&BIT_IBCD_ACTIVATE_CODE_ACT7);
    eval 'sub BIT_IBCD_ACTIVATE_CODE_ACT6 () {0x40;}' unless defined(&BIT_IBCD_ACTIVATE_CODE_ACT6);
    eval 'sub BIT_IBCD_ACTIVATE_CODE_ACT5 () {0x20;}' unless defined(&BIT_IBCD_ACTIVATE_CODE_ACT5);
    eval 'sub BIT_IBCD_ACTIVATE_CODE_ACT4 () {0x10;}' unless defined(&BIT_IBCD_ACTIVATE_CODE_ACT4);
    eval 'sub BIT_IBCD_ACTIVATE_CODE_ACT3 () {0x8;}' unless defined(&BIT_IBCD_ACTIVATE_CODE_ACT3);
    eval 'sub BIT_IBCD_ACTIVATE_CODE_ACT2 () {0x4;}' unless defined(&BIT_IBCD_ACTIVATE_CODE_ACT2);
    eval 'sub BIT_IBCD_ACTIVATE_CODE_ACT1 () {0x2;}' unless defined(&BIT_IBCD_ACTIVATE_CODE_ACT1);
    eval 'sub BIT_IBCD_ACTIVATE_CODE_ACT0 () {0x1;}' unless defined(&BIT_IBCD_ACTIVATE_CODE_ACT0);
    eval 'sub REG_IBCD_DEACTIVATE_CODE () {0x4f;}' unless defined(&REG_IBCD_DEACTIVATE_CODE);
    eval 'sub BIT_IBCD_DEACTIVATE_CODE_DACT7 () {0x80;}' unless defined(&BIT_IBCD_DEACTIVATE_CODE_DACT7);
    eval 'sub BIT_IBCD_DEACTIVATE_CODE_DACT6 () {0x40;}' unless defined(&BIT_IBCD_DEACTIVATE_CODE_DACT6);
    eval 'sub BIT_IBCD_DEACTIVATE_CODE_DACT5 () {0x20;}' unless defined(&BIT_IBCD_DEACTIVATE_CODE_DACT5);
    eval 'sub BIT_IBCD_DEACTIVATE_CODE_DACT4 () {0x10;}' unless defined(&BIT_IBCD_DEACTIVATE_CODE_DACT4);
    eval 'sub BIT_IBCD_DEACTIVATE_CODE_DACT3 () {0x8;}' unless defined(&BIT_IBCD_DEACTIVATE_CODE_DACT3);
    eval 'sub BIT_IBCD_DEACTIVATE_CODE_DACT2 () {0x4;}' unless defined(&BIT_IBCD_DEACTIVATE_CODE_DACT2);
    eval 'sub BIT_IBCD_DEACTIVATE_CODE_DACT1 () {0x2;}' unless defined(&BIT_IBCD_DEACTIVATE_CODE_DACT1);
    eval 'sub BIT_IBCD_DEACTIVATE_CODE_DACT0 () {0x1;}' unless defined(&BIT_IBCD_DEACTIVATE_CODE_DACT0);
    eval 'sub REG_PMON_INT_EN_STATUS () {0x58;}' unless defined(&REG_PMON_INT_EN_STATUS);
    eval 'sub BIT_PMON_INT_EN_STATUS_INTE () {0x4;}' unless defined(&BIT_PMON_INT_EN_STATUS_INTE);
    eval 'sub BIT_PMON_INT_EN_STATUS_XFER () {0x2;}' unless defined(&BIT_PMON_INT_EN_STATUS_XFER);
    eval 'sub BIT_PMON_INT_EN_STATUS_OVR () {0x1;}' unless defined(&BIT_PMON_INT_EN_STATUS_OVR);
    eval 'sub REG_T1_ALMI_INT_EN () {0x61;}' unless defined(&REG_T1_ALMI_INT_EN);
    eval 'sub BIT_T1_ALMI_INT_EN_FASTD () {0x10;}' unless defined(&BIT_T1_ALMI_INT_EN_FASTD);
    eval 'sub BIT_T1_ALMI_INT_EN_ACCEL () {0x8;}' unless defined(&BIT_T1_ALMI_INT_EN_ACCEL);
    eval 'sub BIT_T1_ALMI_INT_EN_YELE () {0x4;}' unless defined(&BIT_T1_ALMI_INT_EN_YELE);
    eval 'sub BIT_T1_ALMI_INT_EN_REDE () {0x2;}' unless defined(&BIT_T1_ALMI_INT_EN_REDE);
    eval 'sub BIT_T1_ALMI_INT_EN_AISE () {0x1;}' unless defined(&BIT_T1_ALMI_INT_EN_AISE);
    eval 'sub REG_T1_ALMI_INT_STATUS () {0x62;}' unless defined(&REG_T1_ALMI_INT_STATUS);
    eval 'sub BIT_T1_ALMI_INT_STATUS_YELI () {0x20;}' unless defined(&BIT_T1_ALMI_INT_STATUS_YELI);
    eval 'sub BIT_T1_ALMI_INT_STATUS_REDI () {0x10;}' unless defined(&BIT_T1_ALMI_INT_STATUS_REDI);
    eval 'sub BIT_T1_ALMI_INT_STATUS_AISI () {0x8;}' unless defined(&BIT_T1_ALMI_INT_STATUS_AISI);
    eval 'sub BIT_T1_ALMI_INT_STATUS_YEL () {0x4;}' unless defined(&BIT_T1_ALMI_INT_STATUS_YEL);
    eval 'sub BIT_T1_ALMI_INT_STATUS_RED () {0x2;}' unless defined(&BIT_T1_ALMI_INT_STATUS_RED);
    eval 'sub BIT_T1_ALMI_INT_STATUS_AIS () {0x1;}' unless defined(&BIT_T1_ALMI_INT_STATUS_AIS);
    eval 'sub REG_PDVD_INT_EN_STATUS () {0x65;}' unless defined(&REG_PDVD_INT_EN_STATUS);
    eval 'sub BIT_PDVD_INT_EN_STATUS_PDV () {0x10;}' unless defined(&BIT_PDVD_INT_EN_STATUS_PDV);
    eval 'sub BIT_PDVD_INT_EN_STATUS_Z16DI () {0x8;}' unless defined(&BIT_PDVD_INT_EN_STATUS_Z16DI);
    eval 'sub BIT_PDVD_INT_EN_STATUS_PDVI () {0x4;}' unless defined(&BIT_PDVD_INT_EN_STATUS_PDVI);
    eval 'sub BIT_PDVD_INT_EN_STATUS_Z16DE () {0x2;}' unless defined(&BIT_PDVD_INT_EN_STATUS_Z16DE);
    eval 'sub BIT_PDVD_INT_EN_STATUS_PDVE () {0x1;}' unless defined(&BIT_PDVD_INT_EN_STATUS_PDVE);
    eval 'sub REG_XPDE_INT_EN_STATUS () {0x69;}' unless defined(&REG_XPDE_INT_EN_STATUS);
    eval 'sub BIT_XPDE_INT_EN_STATUS_STUFE () {0x80;}' unless defined(&BIT_XPDE_INT_EN_STATUS_STUFE);
    eval 'sub BIT_XPDE_INT_EN_STATUS_STUFF () {0x40;}' unless defined(&BIT_XPDE_INT_EN_STATUS_STUFF);
    eval 'sub BIT_XPDE_INT_EN_STATUS_STUFI () {0x20;}' unless defined(&BIT_XPDE_INT_EN_STATUS_STUFI);
    eval 'sub BIT_XPDE_INT_EN_STATUS_PDV () {0x10;}' unless defined(&BIT_XPDE_INT_EN_STATUS_PDV);
    eval 'sub BIT_XPDE_INT_EN_STATUS_Z16DI () {0x8;}' unless defined(&BIT_XPDE_INT_EN_STATUS_Z16DI);
    eval 'sub BIT_XPDE_INT_EN_STATUS_PDVI () {0x4;}' unless defined(&BIT_XPDE_INT_EN_STATUS_PDVI);
    eval 'sub BIT_XPDE_INT_EN_STATUS_Z16DE () {0x2;}' unless defined(&BIT_XPDE_INT_EN_STATUS_Z16DE);
    eval 'sub BIT_XPDE_INT_EN_STATUS_PDVE () {0x1;}' unless defined(&BIT_XPDE_INT_EN_STATUS_PDVE);
    eval 'sub REG_T1_APRM_INT_STATUS () {0x7a;}' unless defined(&REG_T1_APRM_INT_STATUS);
    eval 'sub BIT_T1_APRM_INT_STATUS_INTR () {0x1;}' unless defined(&BIT_T1_APRM_INT_STATUS_INTR);
    eval 'sub REG_E1_TRAN_INT_EN () {0x84;}' unless defined(&REG_E1_TRAN_INT_EN);
    eval 'sub BIT_E1_TRAN_INT_EN_SIGMFE () {0x10;}' unless defined(&BIT_E1_TRAN_INT_EN_SIGMFE);
    eval 'sub BIT_E1_TRAN_INT_EN_NFASE () {0x8;}' unless defined(&BIT_E1_TRAN_INT_EN_NFASE);
    eval 'sub BIT_E1_TRAN_INT_EN_MFE () {0x4;}' unless defined(&BIT_E1_TRAN_INT_EN_MFE);
    eval 'sub BIT_E1_TRAN_INT_EN_SMFE () {0x2;}' unless defined(&BIT_E1_TRAN_INT_EN_SMFE);
    eval 'sub BIT_E1_TRAN_INT_EN_FRME () {0x1;}' unless defined(&BIT_E1_TRAN_INT_EN_FRME);
    eval 'sub REG_E1_TRAN_INT_STATUS () {0x85;}' unless defined(&REG_E1_TRAN_INT_STATUS);
    eval 'sub BIT_E1_TRAN_INT_STATUS_SIGMFI () {0x10;}' unless defined(&BIT_E1_TRAN_INT_STATUS_SIGMFI);
    eval 'sub BIT_E1_TRAN_INT_STATUS_NFASI () {0x8;}' unless defined(&BIT_E1_TRAN_INT_STATUS_NFASI);
    eval 'sub BIT_E1_TRAN_INT_STATUS_MFI () {0x4;}' unless defined(&BIT_E1_TRAN_INT_STATUS_MFI);
    eval 'sub BIT_E1_TRAN_INT_STATUS_SMFI () {0x2;}' unless defined(&BIT_E1_TRAN_INT_STATUS_SMFI);
    eval 'sub BIT_E1_TRAN_INT_STATUS_FRMI () {0x1;}' unless defined(&BIT_E1_TRAN_INT_STATUS_FRMI);
    eval 'sub REG_E1_FRMR_FRM_STAT_INT_EN () {0x92;}' unless defined(&REG_E1_FRMR_FRM_STAT_INT_EN);
    eval 'sub BIT_E1_FRMR_FRM_STAT_INT_EN_C2NCIWE () {0x80;}' unless defined(&BIT_E1_FRMR_FRM_STAT_INT_EN_C2NCIWE);
    eval 'sub BIT_E1_FRMR_FRM_STAT_INT_EN_OOFE () {0x40;}' unless defined(&BIT_E1_FRMR_FRM_STAT_INT_EN_OOFE);
    eval 'sub BIT_E1_FRMR_FRM_STAT_INT_EN_OOSMFE () {0x20;}' unless defined(&BIT_E1_FRMR_FRM_STAT_INT_EN_OOSMFE);
    eval 'sub BIT_E1_FRMR_FRM_STAT_INT_EN_OOCMFE () {0x10;}' unless defined(&BIT_E1_FRMR_FRM_STAT_INT_EN_OOCMFE);
    eval 'sub BIT_E1_FRMR_FRM_STAT_INT_EN_COFAE () {0x8;}' unless defined(&BIT_E1_FRMR_FRM_STAT_INT_EN_COFAE);
    eval 'sub BIT_E1_FRMR_FRM_STAT_INT_EN_FERE () {0x4;}' unless defined(&BIT_E1_FRMR_FRM_STAT_INT_EN_FERE);
    eval 'sub BIT_E1_FRMR_FRM_STAT_INT_EN_SMFERE () {0x2;}' unless defined(&BIT_E1_FRMR_FRM_STAT_INT_EN_SMFERE);
    eval 'sub BIT_E1_FRMR_FRM_STAT_INT_EN_CMFERE () {0x1;}' unless defined(&BIT_E1_FRMR_FRM_STAT_INT_EN_CMFERE);
    eval 'sub REG_E1_FRMR_M_A_INT_EN () {0x93;}' unless defined(&REG_E1_FRMR_M_A_INT_EN);
    eval 'sub BIT_E1_FRMR_M_A_INT_EN_RAIE () {0x80;}' unless defined(&BIT_E1_FRMR_M_A_INT_EN_RAIE);
    eval 'sub BIT_E1_FRMR_M_A_INT_EN_RMAIE () {0x40;}' unless defined(&BIT_E1_FRMR_M_A_INT_EN_RMAIE);
    eval 'sub BIT_E1_FRMR_M_A_INT_EN_AISDE () {0x20;}' unless defined(&BIT_E1_FRMR_M_A_INT_EN_AISDE);
    eval 'sub BIT_E1_FRMR_M_A_INT_EN_REDE () {0x8;}' unless defined(&BIT_E1_FRMR_M_A_INT_EN_REDE);
    eval 'sub BIT_E1_FRMR_M_A_INT_EN_AISE () {0x4;}' unless defined(&BIT_E1_FRMR_M_A_INT_EN_AISE);
    eval 'sub BIT_E1_FRMR_M_A_INT_EN_FEBEE () {0x2;}' unless defined(&BIT_E1_FRMR_M_A_INT_EN_FEBEE);
    eval 'sub BIT_E1_FRMR_M_A_INT_EN_CRCEE () {0x1;}' unless defined(&BIT_E1_FRMR_M_A_INT_EN_CRCEE);
    eval 'sub REG_E1_FRMR_FRM_STAT_INT_IND () {0x94;}' unless defined(&REG_E1_FRMR_FRM_STAT_INT_IND);
    eval 'sub BIT_E1_FRMR_FRM_STAT_INT_IND_C2NCIWI () {0x80;}' unless defined(&BIT_E1_FRMR_FRM_STAT_INT_IND_C2NCIWI);
    eval 'sub BIT_E1_FRMR_FRM_STAT_INT_IND_OOFI () {0x40;}' unless defined(&BIT_E1_FRMR_FRM_STAT_INT_IND_OOFI);
    eval 'sub BIT_E1_FRMR_FRM_STAT_INT_IND_OOSMFI () {0x20;}' unless defined(&BIT_E1_FRMR_FRM_STAT_INT_IND_OOSMFI);
    eval 'sub BIT_E1_FRMR_FRM_STAT_INT_IND_OOCMFI () {0x10;}' unless defined(&BIT_E1_FRMR_FRM_STAT_INT_IND_OOCMFI);
    eval 'sub BIT_E1_FRMR_FRM_STAT_INT_IND_COFAI () {0x8;}' unless defined(&BIT_E1_FRMR_FRM_STAT_INT_IND_COFAI);
    eval 'sub BIT_E1_FRMR_FRM_STAT_INT_IND_FERI () {0x4;}' unless defined(&BIT_E1_FRMR_FRM_STAT_INT_IND_FERI);
    eval 'sub BIT_E1_FRMR_FRM_STAT_INT_IND_SMFERI () {0x2;}' unless defined(&BIT_E1_FRMR_FRM_STAT_INT_IND_SMFERI);
    eval 'sub BIT_E1_FRMR_FRM_STAT_INT_IND_CMFERI () {0x1;}' unless defined(&BIT_E1_FRMR_FRM_STAT_INT_IND_CMFERI);
    eval 'sub REG_E1_FRMR_M_A_INT_IND () {0x95;}' unless defined(&REG_E1_FRMR_M_A_INT_IND);
    eval 'sub BIT_E1_FRMR_M_A_INT_IND_RAII () {0x80;}' unless defined(&BIT_E1_FRMR_M_A_INT_IND_RAII);
    eval 'sub BIT_E1_FRMR_M_A_INT_IND_FMAII () {0x40;}' unless defined(&BIT_E1_FRMR_M_A_INT_IND_FMAII);
    eval 'sub BIT_E1_FRMR_M_A_INT_IND_AISDI () {0x20;}' unless defined(&BIT_E1_FRMR_M_A_INT_IND_AISDI);
    eval 'sub BIT_E1_FRMR_M_A_INT_IND_REDI () {0x8;}' unless defined(&BIT_E1_FRMR_M_A_INT_IND_REDI);
    eval 'sub BIT_E1_FRMR_M_A_INT_IND_AISI () {0x4;}' unless defined(&BIT_E1_FRMR_M_A_INT_IND_AISI);
    eval 'sub BIT_E1_FRMR_M_A_INT_IND_FEBEI () {0x2;}' unless defined(&BIT_E1_FRMR_M_A_INT_IND_FEBEI);
    eval 'sub BIT_E1_FRMR_M_A_INT_IND_CRCEI () {0x1;}' unless defined(&BIT_E1_FRMR_M_A_INT_IND_CRCEI);
    eval 'sub REG_E1_FRMR_P_A_INT_EN () {0x9e;}' unless defined(&REG_E1_FRMR_P_A_INT_EN);
    eval 'sub BIT_E1_FRMR_P_A_INT_EN_OOOFE () {0x80;}' unless defined(&BIT_E1_FRMR_P_A_INT_EN_OOOFE);
    eval 'sub BIT_E1_FRMR_P_A_INT_EN_RAICCRCE () {0x40;}' unless defined(&BIT_E1_FRMR_P_A_INT_EN_RAICCRCE);
    eval 'sub BIT_E1_FRMR_P_A_INT_EN_CFEBEE () {0x20;}' unless defined(&BIT_E1_FRMR_P_A_INT_EN_CFEBEE);
    eval 'sub BIT_E1_FRMR_P_A_INT_EN_V52LINKE () {0x10;}' unless defined(&BIT_E1_FRMR_P_A_INT_EN_V52LINKE);
    eval 'sub BIT_E1_FRMR_P_A_INT_EN_IFPE () {0x8;}' unless defined(&BIT_E1_FRMR_P_A_INT_EN_IFPE);
    eval 'sub BIT_E1_FRMR_P_A_INT_EN_ICSMFPE () {0x4;}' unless defined(&BIT_E1_FRMR_P_A_INT_EN_ICSMFPE);
    eval 'sub BIT_E1_FRMR_P_A_INT_EN_ICMFPE () {0x2;}' unless defined(&BIT_E1_FRMR_P_A_INT_EN_ICMFPE);
    eval 'sub BIT_E1_FRMR_P_A_INT_EN_ISMFPE () {0x1;}' unless defined(&BIT_E1_FRMR_P_A_INT_EN_ISMFPE);
    eval 'sub REG_E1_FRMR_P_A_INT_STAT () {0x9f;}' unless defined(&REG_E1_FRMR_P_A_INT_STAT);
    eval 'sub BIT_E1_FRMR_P_A_INT_STAT_OOOFI () {0x80;}' unless defined(&BIT_E1_FRMR_P_A_INT_STAT_OOOFI);
    eval 'sub BIT_E1_FRMR_P_A_INT_STAT_RAICCRCI () {0x40;}' unless defined(&BIT_E1_FRMR_P_A_INT_STAT_RAICCRCI);
    eval 'sub BIT_E1_FRMR_P_A_INT_STAT_CFEBEI () {0x20;}' unless defined(&BIT_E1_FRMR_P_A_INT_STAT_CFEBEI);
    eval 'sub BIT_E1_FRMR_P_A_INT_STAT_V52LINKI () {0x10;}' unless defined(&BIT_E1_FRMR_P_A_INT_STAT_V52LINKI);
    eval 'sub BIT_E1_FRMR_P_A_INT_STAT_IFPI () {0x8;}' unless defined(&BIT_E1_FRMR_P_A_INT_STAT_IFPI);
    eval 'sub BIT_E1_FRMR_P_A_INT_STAT_ICSMFPI () {0x4;}' unless defined(&BIT_E1_FRMR_P_A_INT_STAT_ICSMFPI);
    eval 'sub BIT_E1_FRMR_P_A_INT_STAT_ICMFPI () {0x2;}' unless defined(&BIT_E1_FRMR_P_A_INT_STAT_ICMFPI);
    eval 'sub BIT_E1_FRMR_P_A_INT_STAT_ISMFPI () {0x1;}' unless defined(&BIT_E1_FRMR_P_A_INT_STAT_ISMFPI);
    eval 'sub WAN_LC_AMI () {0x1;}' unless defined(&WAN_LC_AMI);
    eval 'sub WAN_LC_B8ZS () {0x2;}' unless defined(&WAN_LC_B8ZS);
    eval 'sub WAN_LC_HDB3 () {0x3;}' unless defined(&WAN_LC_HDB3);
    eval 'sub WAN_FR_ESF () {0x1;}' unless defined(&WAN_FR_ESF);
    eval 'sub WAN_FR_D4 () {0x2;}' unless defined(&WAN_FR_D4);
    eval 'sub WAN_FR_ESF_JAPAN () {0x3;}' unless defined(&WAN_FR_ESF_JAPAN);
    eval 'sub WAN_FR_CRC4 () {0x4;}' unless defined(&WAN_FR_CRC4);
    eval 'sub WAN_FR_NCRC4 () {0x5;}' unless defined(&WAN_FR_NCRC4);
    eval 'sub WAN_FR_UNFRAMED () {0x6;}' unless defined(&WAN_FR_UNFRAMED);
    eval 'sub WAN_T1_LBO_0_DB () {0x1;}' unless defined(&WAN_T1_LBO_0_DB);
    eval 'sub WAN_T1_LBO_75_DB () {0x2;}' unless defined(&WAN_T1_LBO_75_DB);
    eval 'sub WAN_T1_LBO_15_DB () {0x3;}' unless defined(&WAN_T1_LBO_15_DB);
    eval 'sub WAN_T1_LBO_225_DB () {0x4;}' unless defined(&WAN_T1_LBO_225_DB);
    eval 'sub WAN_T1_0_110 () {0x5;}' unless defined(&WAN_T1_0_110);
    eval 'sub WAN_T1_110_220 () {0x6;}' unless defined(&WAN_T1_110_220);
    eval 'sub WAN_T1_220_330 () {0x7;}' unless defined(&WAN_T1_220_330);
    eval 'sub WAN_T1_330_440 () {0x8;}' unless defined(&WAN_T1_330_440);
    eval 'sub WAN_T1_440_550 () {0x9;}' unless defined(&WAN_T1_440_550);
    eval 'sub WAN_T1_550_660 () {0xa;}' unless defined(&WAN_T1_550_660);
    eval 'sub WAN_E1_120 () {0xb;}' unless defined(&WAN_E1_120);
    eval 'sub WAN_E1_75 () {0xc;}' unless defined(&WAN_E1_75);
    eval 'sub WAN_NORMAL_CLK () {0x1;}' unless defined(&WAN_NORMAL_CLK);
    eval 'sub WAN_MASTER_CLK () {0x2;}' unless defined(&WAN_MASTER_CLK);
    eval 'sub NUM_OF_T1_CHANNELS () {24;}' unless defined(&NUM_OF_T1_CHANNELS);
    eval 'sub NUM_OF_E1_TIMESLOTS () {31;}' unless defined(&NUM_OF_E1_TIMESLOTS);
    eval 'sub NUM_OF_E1_CHANNELS () {32;}' unless defined(&NUM_OF_E1_CHANNELS);
    eval 'sub ENABLE_ALL_CHANNELS () {0xffffffff;}' unless defined(&ENABLE_ALL_CHANNELS);
    eval 'sub E1_FRAMING_TIMESLOT () {0;}' unless defined(&E1_FRAMING_TIMESLOT);
    eval 'sub E1_SIGNALING_TIMESLOT () {16;}' unless defined(&E1_SIGNALING_TIMESLOT);
    eval 'sub BIT_ALOS_ALARM () {0x1;}' unless defined(&BIT_ALOS_ALARM);
    eval 'sub BIT_LOS_ALARM () {0x2;}' unless defined(&BIT_LOS_ALARM);
    eval 'sub BIT_ALTLOS_ALARM () {0x4;}' unless defined(&BIT_ALTLOS_ALARM);
    eval 'sub BIT_OOF_ALARM () {0x8;}' unless defined(&BIT_OOF_ALARM);
    eval 'sub BIT_RED_ALARM () {0x10;}' unless defined(&BIT_RED_ALARM);
    eval 'sub BIT_AIS_ALARM () {0x20;}' unless defined(&BIT_AIS_ALARM);
    eval 'sub BIT_OOSMF_ALARM () {0x40;}' unless defined(&BIT_OOSMF_ALARM);
    eval 'sub BIT_OOCMF_ALARM () {0x80;}' unless defined(&BIT_OOCMF_ALARM);
    eval 'sub BIT_OOOF_ALARM () {0x100;}' unless defined(&BIT_OOOF_ALARM);
    eval 'sub BIT_RAI_ALARM () {0x200;}' unless defined(&BIT_RAI_ALARM);
    eval 'sub BIT_YEL_ALARM () {0x400;}' unless defined(&BIT_YEL_ALARM);
    eval 'sub BIT_LOOPUP_CODE () {0x2000;}' unless defined(&BIT_LOOPUP_CODE);
    eval 'sub BIT_LOOPDOWN_CODE () {0x4000;}' unless defined(&BIT_LOOPDOWN_CODE);
    eval 'sub BIT_TE1_ALARM () {0x8000;}' unless defined(&BIT_TE1_ALARM);
    eval 'sub frm_bit_error () { &pmon1;}' unless defined(&frm_bit_error);
    eval 'sub oof_errors () { &pmon2;}' unless defined(&oof_errors);
    eval 'sub far_end_blk_errors () { &pmon2;}' unless defined(&far_end_blk_errors);
    eval 'sub bit_errors () { &pmon3;}' unless defined(&bit_errors);
    eval 'sub crc_errors () { &pmon3;}' unless defined(&crc_errors);
    eval 'sub lcv () { &pmon4;}' unless defined(&lcv);
    eval 'sub WAN_TE1_LINELB_MODE () {0x1;}' unless defined(&WAN_TE1_LINELB_MODE);
    eval 'sub WAN_TE1_PAYLB_MODE () {0x2;}' unless defined(&WAN_TE1_PAYLB_MODE);
    eval 'sub WAN_TE1_DDLB_MODE () {0x3;}' unless defined(&WAN_TE1_DDLB_MODE);
    eval 'sub WAN_TE1_TX_LB_MODE () {0x4;}' unless defined(&WAN_TE1_TX_LB_MODE);
    eval 'sub WAN_TE1_ACTIVATE_LB () {0x1;}' unless defined(&WAN_TE1_ACTIVATE_LB);
    eval 'sub WAN_TE1_DEACTIVATE_LB () {0x2;}' unless defined(&WAN_TE1_DEACTIVATE_LB);
    eval 'sub LINELB_TE1_TIMER () {40;}' unless defined(&LINELB_TE1_TIMER);
    eval 'sub LINELB_CODE_CNT () {10;}' unless defined(&LINELB_CODE_CNT);
    eval 'sub LINELB_CHANNEL_CNT () {10;}' unless defined(&LINELB_CHANNEL_CNT);
    eval 'sub LINELB_ACTIVATE_CODE () {0x7;}' unless defined(&LINELB_ACTIVATE_CODE);
    eval 'sub LINELB_DEACTIVATE_CODE () {0x1c;}' unless defined(&LINELB_DEACTIVATE_CODE);
    eval 'sub LINELB_DS3LINE () {0x1b;}' unless defined(&LINELB_DS3LINE);
    eval 'sub LINELB_DS1LINE_1 () {0x21;}' unless defined(&LINELB_DS1LINE_1);
    eval 'sub LINELB_DS1LINE_2 () {0x22;}' unless defined(&LINELB_DS1LINE_2);
    eval 'sub LINELB_DS1LINE_3 () {0x23;}' unless defined(&LINELB_DS1LINE_3);
    eval 'sub LINELB_DS1LINE_4 () {0x24;}' unless defined(&LINELB_DS1LINE_4);
    eval 'sub LINELB_DS1LINE_5 () {0x25;}' unless defined(&LINELB_DS1LINE_5);
    eval 'sub LINELB_DS1LINE_6 () {0x26;}' unless defined(&LINELB_DS1LINE_6);
    eval 'sub LINELB_DS1LINE_7 () {0x27;}' unless defined(&LINELB_DS1LINE_7);
    eval 'sub LINELB_DS1LINE_8 () {0x28;}' unless defined(&LINELB_DS1LINE_8);
    eval 'sub LINELB_DS1LINE_9 () {0x29;}' unless defined(&LINELB_DS1LINE_9);
    eval 'sub LINELB_DS1LINE_10 () {0x2a;}' unless defined(&LINELB_DS1LINE_10);
    eval 'sub LINELB_DS1LINE_11 () {0x2b;}' unless defined(&LINELB_DS1LINE_11);
    eval 'sub LINELB_DS1LINE_12 () {0x2c;}' unless defined(&LINELB_DS1LINE_12);
    eval 'sub LINELB_DS1LINE_13 () {0x2d;}' unless defined(&LINELB_DS1LINE_13);
    eval 'sub LINELB_DS1LINE_14 () {0x2e;}' unless defined(&LINELB_DS1LINE_14);
    eval 'sub LINELB_DS1LINE_15 () {0x2f;}' unless defined(&LINELB_DS1LINE_15);
    eval 'sub LINELB_DS1LINE_16 () {0x30;}' unless defined(&LINELB_DS1LINE_16);
    eval 'sub LINELB_DS1LINE_17 () {0x31;}' unless defined(&LINELB_DS1LINE_17);
    eval 'sub LINELB_DS1LINE_18 () {0x32;}' unless defined(&LINELB_DS1LINE_18);
    eval 'sub LINELB_DS1LINE_19 () {0x33;}' unless defined(&LINELB_DS1LINE_19);
    eval 'sub LINELB_DS1LINE_20 () {0x34;}' unless defined(&LINELB_DS1LINE_20);
    eval 'sub LINELB_DS1LINE_21 () {0x35;}' unless defined(&LINELB_DS1LINE_21);
    eval 'sub LINELB_DS1LINE_22 () {0x36;}' unless defined(&LINELB_DS1LINE_22);
    eval 'sub LINELB_DS1LINE_23 () {0x37;}' unless defined(&LINELB_DS1LINE_23);
    eval 'sub LINELB_DS1LINE_24 () {0x38;}' unless defined(&LINELB_DS1LINE_24);
    eval 'sub LINELB_DS1LINE_25 () {0x39;}' unless defined(&LINELB_DS1LINE_25);
    eval 'sub LINELB_DS1LINE_26 () {0x3a;}' unless defined(&LINELB_DS1LINE_26);
    eval 'sub LINELB_DS1LINE_27 () {0x3b;}' unless defined(&LINELB_DS1LINE_27);
    eval 'sub LINELB_DS1LINE_28 () {0x3c;}' unless defined(&LINELB_DS1LINE_28);
    eval 'sub LINELB_DS1LINE_ALL () {0x13;}' unless defined(&LINELB_DS1LINE_ALL);
    eval 'sub LINELB_DS1LINE_MASK () {0x1f;}' unless defined(&LINELB_DS1LINE_MASK);
    eval 'sub POLLING_TE1_TIMER () {1000;}' unless defined(&POLLING_TE1_TIMER);
    eval 'sub TE_TIMER_RUNNING () {0x1;}' unless defined(&TE_TIMER_RUNNING);
    eval 'sub TE_TIMER_KILL () {0x2;}' unless defined(&TE_TIMER_KILL);
    eval 'sub LINELB_WAITING () {0x3;}' unless defined(&LINELB_WAITING);
    eval 'sub LINELB_CODE_BIT () {0x4;}' unless defined(&LINELB_CODE_BIT);
    eval 'sub LINELB_CHANNEL_BIT () {0x5;}' unless defined(&LINELB_CHANNEL_BIT);
    eval 'sub TE_CONFIGURED () {0x6;}' unless defined(&TE_CONFIGURED);
    if(0) {
	eval 'sub TE_TIMER_RUNNING () {0x1;}' unless defined(&TE_TIMER_RUNNING);
	eval 'sub TE_TIMER_KILL () {0x2;}' unless defined(&TE_TIMER_KILL);
	eval 'sub LINELB_WAITING () {0x4;}' unless defined(&LINELB_WAITING);
	eval 'sub LINELB_CODE_BIT () {0x8;}' unless defined(&LINELB_CODE_BIT);
	eval 'sub LINELB_CHANNEL_BIT () {0x10;}' unless defined(&LINELB_CHANNEL_BIT);
    }
    eval 'sub TE_LINELB_TIMER () {0x1;}' unless defined(&TE_LINELB_TIMER);
    eval 'sub TE_LINKDOWN_TIMER () {0x2;}' unless defined(&TE_LINKDOWN_TIMER);
    eval 'sub TE_SET_INTR () {0x3;}' unless defined(&TE_SET_INTR);
    eval 'sub TE_ABCD_UPDATE () {0x4;}' unless defined(&TE_ABCD_UPDATE);
    eval 'sub TE_LINKUP_TIMER () {0x5;}' unless defined(&TE_LINKUP_TIMER);
    eval 'sub INTR_TE1_TIMER () {150;}' unless defined(&INTR_TE1_TIMER);
    eval 'sub IS_T1 {
        my($te_cfg) = @_;
	    eval q((($te_cfg)-> &media ==  &WAN_MEDIA_T1));
    }' unless defined(&IS_T1);
    eval 'sub IS_E1 {
        my($te_cfg) = @_;
	    eval q((($te_cfg)-> &media ==  &WAN_MEDIA_E1));
    }' unless defined(&IS_E1);
    eval 'sub IS_TE1 {
        my($te_cfg) = @_;
	    eval q(( &IS_T1($te_cfg) ||  &IS_E1($te_cfg)));
    }' unless defined(&IS_TE1);
    eval 'sub IS_TE1_UNFRAMED {
        my($card) = @_;
	    eval q((($card)-> ($te_cfg->{frame}) ==  &WAN_FR_UNFRAMED));
    }' unless defined(&IS_TE1_UNFRAMED);
    eval 'sub GET_TE_CHANNEL_RANGE {
        my($card) = @_;
	    eval q(( &IS_T1( ($card->{te_cfg})) ?  &NUM_OF_T1_CHANNELS :  &IS_E1( ($card->{te_cfg})) ?  &NUM_OF_E1_CHANNELS :0));
    }' unless defined(&GET_TE_CHANNEL_RANGE);
    eval 'sub ALOS_ALARM {
        my($val) = @_;
	    eval q(($val &  &BIT_ALOS_ALARM) ? \\"ON\\" : \\"OFF\\");
    }' unless defined(&ALOS_ALARM);
    eval 'sub LOS_ALARM {
        my($val) = @_;
	    eval q(($val &  &BIT_LOS_ALARM) ? \\"ON\\" : \\"OFF\\");
    }' unless defined(&LOS_ALARM);
    eval 'sub ALTLOS_ALARM {
        my($val) = @_;
	    eval q(($val &  &BIT_ALTLOS_ALARM) ? \\"ON\\" : \\"OFF\\");
    }' unless defined(&ALTLOS_ALARM);
    eval 'sub OOF_ALARM {
        my($val) = @_;
	    eval q(($val &  &BIT_OOF_ALARM) ? \\"ON\\" : \\"OFF\\");
    }' unless defined(&OOF_ALARM);
    eval 'sub RED_ALARM {
        my($val) = @_;
	    eval q(($val &  &BIT_RED_ALARM) ? \\"ON\\" : \\"OFF\\");
    }' unless defined(&RED_ALARM);
    eval 'sub AIS_ALARM {
        my($val) = @_;
	    eval q(($val &  &BIT_AIS_ALARM) ? \\"ON\\" : \\"OFF\\");
    }' unless defined(&AIS_ALARM);
    eval 'sub OOSMF_ALARM {
        my($val) = @_;
	    eval q(($val &  &BIT_OOSMF_ALARM) ? \\"ON\\" : \\"OFF\\");
    }' unless defined(&OOSMF_ALARM);
    eval 'sub OOCMF_ALARM {
        my($val) = @_;
	    eval q(($val &  &BIT_OOCMF_ALARM) ? \\"ON\\" : \\"OFF\\");
    }' unless defined(&OOCMF_ALARM);
    eval 'sub OOOF_ALARM {
        my($val) = @_;
	    eval q(($val &  &BIT_OOOF_ALARM) ? \\"ON\\" : \\"OFF\\");
    }' unless defined(&OOOF_ALARM);
    eval 'sub RAI_ALARM {
        my($val) = @_;
	    eval q(($val &  &BIT_RAI_ALARM) ? \\"ON\\" : \\"OFF\\");
    }' unless defined(&RAI_ALARM);
    eval 'sub YEL_ALARM {
        my($val) = @_;
	    eval q(($val &  &BIT_YEL_ALARM) ? \\"ON\\" : \\"OFF\\");
    }' unless defined(&YEL_ALARM);
    eval 'sub MEDIA_DECODE {
        my($val) = @_;
	    eval q(($val ==  &WAN_MEDIA_T1) ? \\"T1\\" : ($val ==  &WAN_MEDIA_E1) ? \\"E1\\" : \\"Unknown\\");
    }' unless defined(&MEDIA_DECODE);
    eval 'sub LCODE_DECODE {
        my($val) = @_;
	    eval q(($val ==  &WAN_LC_AMI) ? \\"AMI\\" : ($val ==  &WAN_LC_B8ZS) ? \\"B8ZS\\" : ($val ==  &WAN_LC_HDB3) ? \\"HDB3\\" : \\"Unknown\\");
    }' unless defined(&LCODE_DECODE);
    eval 'sub FRAME_DECODE {
        my($val) = @_;
	    eval q(($val ==  &WAN_FR_ESF) ? \\"ESF\\" : ($val ==  &WAN_FR_D4) ? \\"D4\\" : ($val ==  &WAN_FR_CRC4) ? \\"CRC4\\" : ($val ==  &WAN_FR_NCRC4) ? \\"non-CRC4\\" : ($val ==  &WAN_FR_UNFRAMED) ? \\"Unframed\\" : \\"Unknown\\");
    }' unless defined(&FRAME_DECODE);
    eval 'sub TECLK_DECODE {
        my($val) = @_;
	    eval q(($val ==  &WAN_NORMAL_CLK) ? \\"Normal\\" : ($val ==  &WAN_MASTER_CLK) ? \\"Master\\" : \\"Unknown\\");
    }' unless defined(&TECLK_DECODE);
    eval 'sub LBO_DECODE {
        my($val) = @_;
	    eval q(($val ==  &WAN_T1_LBO_0_DB) ? \\"0db\\" : ($val ==  &WAN_T1_LBO_75_DB) ? \\"7.5db\\" : ($val ==  &WAN_T1_LBO_15_DB) ? \\"15dB\\" : ($val ==  &WAN_T1_LBO_225_DB) ? \\"22.5dB\\" : ($val ==  &WAN_T1_0_110) ? \\"0-110ft\\" : ($val ==  &WAN_T1_110_220) ? \\"110-220ft\\" : ($val ==  &WAN_T1_220_330) ? \\"220-330ft\\" : ($val ==  &WAN_T1_330_440) ? \\"330-440ft\\" : ($val ==  &WAN_T1_440_550) ? \\"440-550ft\\" : ($val ==  &WAN_T1_550_660) ? \\"550-660ft\\" : \\"Unknown\\");
    }' unless defined(&LBO_DECODE);
    if(defined(&_KERNEL)) {
	eval 'sub TE_SIG_DISABLED () {0x;}' unless defined(&TE_SIG_DISABLED);
	eval 'sub TE_RX_SIG_ENABLED () {0x1;}' unless defined(&TE_RX_SIG_ENABLED);
	eval 'sub TE_TX_SIG_ENABLED () {0x2;}' unless defined(&TE_TX_SIG_ENABLED);
	eval 'sub TE_SET_TX_SIG_BITS () {0x80;}' unless defined(&TE_SET_TX_SIG_BITS);
    }
    undef(&EXTERN) if defined(&EXTERN);
}
1;
