# Verilog language definition file
#
# Author: Andre Simon
#   Mail: andre.simon1@gmx.de
#   Date: 13.04.2004
# ------------------------------------------
# This file is a part of highlight, a free source code converter released under the GPL.
#
# The file is used to describe keywords and special symbols of programming languages.
# See README in the highlight directory for details.
#
# New definition files for future releases of highlight are always appreciated ;)
#
# ----------
# andre.simon1@gmx.de
# http:/www.andre-simon.de/

$KW_LIST(kwa)=always and assign attribute begin buf bufif0 bufif1 case casex casez cmos deassign default defparam disable edge else end endattribute
endcase endmodule endfunction endprimitive endspecify endtable endtask event for force forever fork function highz0 highz1 if initial
inout input integer join large macromodule medium module nand negedge nmos nor not notif0 notif1 or output parameter pmos posedge
primitive pull0 pull1 pullup pulldown rcmos reg release repeat rnmos rpmos rtran rtranif0 rtranif1 scalared small specify specparam
strength strong0 strong1 supply0 supply1 table task time tran tranif0 tranif1 tri tri0 tri1 triand trior trireg use vectored wait wand
weak0 weak1 while wire wor xnor xor

#$KW_PREFIX(kwb)=$
$KW_RE(kwb)=regex(\$\S+)

$STRINGDELIMITERS=" '

$SL_COMMENT=//

$ML_COMMENT=/* */

$ALLOWNESTEDCOMMENTS=false

$IGNORECASE=false

$DIRECTIVE=`

$ESCCHAR=\

$SYMBOLS= ( ) [ ] { } , ; : & | < > !  = / * %  + -
