require '_h2ph_pre.ph';

no warnings qw(redefine misc);

unless(defined(&GCU_REG_H)) {
    eval 'sub GCU_REG_H () {1;}' unless defined(&GCU_REG_H);
    eval 'sub MDIO_STATUS_REG () {0x10;}' unless defined(&MDIO_STATUS_REG);
    eval 'sub MDIO_COMMAND_REG () {0x14;}' unless defined(&MDIO_COMMAND_REG);
    eval 'sub MDIO_STATUS_STATUS_MASK () {0x80000000;}' unless defined(&MDIO_STATUS_STATUS_MASK);
    eval 'sub MDIO_STATUS_READ_DATA_MASK () {0xffff;}' unless defined(&MDIO_STATUS_READ_DATA_MASK);
    eval 'sub MDIO_COMMAND_GO_MASK () {0x80000000;}' unless defined(&MDIO_COMMAND_GO_MASK);
    eval 'sub MDIO_COMMAND_OPER_MASK () {0x4000000;}' unless defined(&MDIO_COMMAND_OPER_MASK);
    eval 'sub MDIO_COMMAND_PHY_ADDR_MASK () {0x3e00000;}' unless defined(&MDIO_COMMAND_PHY_ADDR_MASK);
    eval 'sub MDIO_COMMAND_PHY_REG_MASK () {0x1f0000;}' unless defined(&MDIO_COMMAND_PHY_REG_MASK);
    eval 'sub MDIO_COMMAND_WRITE_DATA_MASK () {0xffff;}' unless defined(&MDIO_COMMAND_WRITE_DATA_MASK);
    eval 'sub MDIO_COMMAND_GO_OFFSET () {31;}' unless defined(&MDIO_COMMAND_GO_OFFSET);
    eval 'sub MDIO_COMMAND_OPER_OFFSET () {26;}' unless defined(&MDIO_COMMAND_OPER_OFFSET);
    eval 'sub MDIO_COMMAND_PHY_ADDR_OFFSET () {21;}' unless defined(&MDIO_COMMAND_PHY_ADDR_OFFSET);
    eval 'sub MDIO_COMMAND_PHY_REG_OFFSET () {16;}' unless defined(&MDIO_COMMAND_PHY_REG_OFFSET);
    eval 'sub MDIO_COMMAND_WRITE_DATA_OFFSET () {0;}' unless defined(&MDIO_COMMAND_WRITE_DATA_OFFSET);
    eval 'sub MDIO_COMMAND_PHY_ADDR_MAX () {2;}' unless defined(&MDIO_COMMAND_PHY_ADDR_MAX);
    eval 'sub MDIO_COMMAND_PHY_REG_MAX () {31;}' unless defined(&MDIO_COMMAND_PHY_REG_MAX);
}
1;
