require '_h2ph_pre.ph';

no warnings qw(redefine misc);

unless(defined(&_MACHINE_FSR_H_)) {
    eval 'sub _MACHINE_FSR_H_ () {1;}' unless defined(&_MACHINE_FSR_H_);
    eval 'sub FPRS_FEF () {0x4;}' unless defined(&FPRS_FEF);
    eval 'sub FPRS_DU () {0x2;}' unless defined(&FPRS_DU);
    eval 'sub FPRS_DL () {0x1;}' unless defined(&FPRS_DL);
    eval 'sub FSR_RD () {0xc0000000;}' unless defined(&FSR_RD);
    eval 'sub FSR_RD_RN () {0;}' unless defined(&FSR_RD_RN);
    eval 'sub FSR_RD_RZ () {1;}' unless defined(&FSR_RD_RZ);
    eval 'sub FSR_RD_RP () {2;}' unless defined(&FSR_RD_RP);
    eval 'sub FSR_RD_RM () {3;}' unless defined(&FSR_RD_RM);
    eval 'sub FSR_RD_SHIFT () {30;}' unless defined(&FSR_RD_SHIFT);
    eval 'sub FSR_RD_MASK () {0x3;}' unless defined(&FSR_RD_MASK);
    eval 'sub FSR_RP () {0x30000000;}' unless defined(&FSR_RP);
    eval 'sub FSR_RP_X () {0;}' unless defined(&FSR_RP_X);
    eval 'sub FSR_RP_S () {1;}' unless defined(&FSR_RP_S);
    eval 'sub FSR_RP_D () {2;}' unless defined(&FSR_RP_D);
    eval 'sub FSR_RP_80 () {3;}' unless defined(&FSR_RP_80);
    eval 'sub FSR_RP_SHIFT () {28;}' unless defined(&FSR_RP_SHIFT);
    eval 'sub FSR_RP_MASK () {0x3;}' unless defined(&FSR_RP_MASK);
    eval 'sub FSR_TEM () {0xf800000;}' unless defined(&FSR_TEM);
    eval 'sub FSR_TEM_SHIFT () {23;}' unless defined(&FSR_TEM_SHIFT);
    eval 'sub FSR_TEM_MASK () {0x1f;}' unless defined(&FSR_TEM_MASK);
    eval 'sub FSR_NS () {0x400000;}' unless defined(&FSR_NS);
    eval 'sub FSR_AU () {0x400000;}' unless defined(&FSR_AU);
    eval 'sub FSR_MBZ () {0x300000;}' unless defined(&FSR_MBZ);
    eval 'sub FSR_VER () {0xe0000;}' unless defined(&FSR_VER);
    eval 'sub FSR_VER_SHIFT () {17;}' unless defined(&FSR_VER_SHIFT);
    eval 'sub FSR_VER_MASK () {0x7;}' unless defined(&FSR_VER_MASK);
    eval 'sub FSR_FTT () {0x1c000;}' unless defined(&FSR_FTT);
    eval 'sub FSR_TT_NONE () {0;}' unless defined(&FSR_TT_NONE);
    eval 'sub FSR_TT_IEEE () {1;}' unless defined(&FSR_TT_IEEE);
    eval 'sub FSR_TT_UNFIN () {2;}' unless defined(&FSR_TT_UNFIN);
    eval 'sub FSR_TT_UNIMP () {3;}' unless defined(&FSR_TT_UNIMP);
    eval 'sub FSR_TT_SEQ () {4;}' unless defined(&FSR_TT_SEQ);
    eval 'sub FSR_TT_HWERR () {5;}' unless defined(&FSR_TT_HWERR);
    eval 'sub FSR_FTT_SHIFT () {14;}' unless defined(&FSR_FTT_SHIFT);
    eval 'sub FSR_FTT_MASK () {0x3;}' unless defined(&FSR_FTT_MASK);
    eval 'sub FSR_QNE () {0x2000;}' unless defined(&FSR_QNE);
    eval 'sub FSR_PR () {0x1000;}' unless defined(&FSR_PR);
    eval 'sub FSR_FCC () {0xc00;}' unless defined(&FSR_FCC);
    eval 'sub FSR_CC_EQ () {0;}' unless defined(&FSR_CC_EQ);
    eval 'sub FSR_CC_LT () {1;}' unless defined(&FSR_CC_LT);
    eval 'sub FSR_CC_GT () {2;}' unless defined(&FSR_CC_GT);
    eval 'sub FSR_CC_UO () {3;}' unless defined(&FSR_CC_UO);
    eval 'sub FSR_FCC_SHIFT () {10;}' unless defined(&FSR_FCC_SHIFT);
    eval 'sub FSR_FCC_MASK () {0x3;}' unless defined(&FSR_FCC_MASK);
    eval 'sub FSR_AX () {0x3e0;}' unless defined(&FSR_AX);
    eval 'sub FSR_AX_SHIFT () {5;}' unless defined(&FSR_AX_SHIFT);
    eval 'sub FSR_AX_MASK () {0x1f;}' unless defined(&FSR_AX_MASK);
    eval 'sub FSR_CX () {0x1f;}' unless defined(&FSR_CX);
    eval 'sub FSR_CX_SHIFT () {0;}' unless defined(&FSR_CX_SHIFT);
    eval 'sub FSR_CX_MASK () {0x1f;}' unless defined(&FSR_CX_MASK);
    eval 'sub FSR_FCC3 () {0x6000000000;}' unless defined(&FSR_FCC3);
    eval 'sub FSR_FCC3_SHIFT () {36;}' unless defined(&FSR_FCC3_SHIFT);
    eval 'sub FSR_FCC2 () {0xc00000000;}' unless defined(&FSR_FCC2);
    eval 'sub FSR_FCC2_SHIFT () {34;}' unless defined(&FSR_FCC2_SHIFT);
    eval 'sub FSR_FCC1 () {0x600000000;}' unless defined(&FSR_FCC1);
    eval 'sub FSR_FCC1_SHIFT () {32;}' unless defined(&FSR_FCC1_SHIFT);
    eval 'sub FSR_NV () {0x10;}' unless defined(&FSR_NV);
    eval 'sub FSR_OF () {0x8;}' unless defined(&FSR_OF);
    eval 'sub FSR_UF () {0x4;}' unless defined(&FSR_UF);
    eval 'sub FSR_DZ () {0x2;}' unless defined(&FSR_DZ);
    eval 'sub FSR_NX () {0x1;}' unless defined(&FSR_NX);
}
1;
