require '_h2ph_pre.ph';

no warnings qw(redefine misc);

unless(defined(&_IF_ALCREG_H)) {
    eval 'sub _IF_ALCREG_H () {1;}' unless defined(&_IF_ALCREG_H);
    eval 'sub ALC_PCIR_BAR () {0x10;}' unless defined(&ALC_PCIR_BAR);
    eval 'sub ALC_PEX_UNC_ERR_SEV () {0x10c;}' unless defined(&ALC_PEX_UNC_ERR_SEV);
    eval 'sub PEX_UNC_ERR_SEV_TRN () {0x1;}' unless defined(&PEX_UNC_ERR_SEV_TRN);
    eval 'sub PEX_UNC_ERR_SEV_DLP () {0x10;}' unless defined(&PEX_UNC_ERR_SEV_DLP);
    eval 'sub PEX_UNC_ERR_SEV_PSN_TLP () {0x1000;}' unless defined(&PEX_UNC_ERR_SEV_PSN_TLP);
    eval 'sub PEX_UNC_ERR_SEV_FCP () {0x2000;}' unless defined(&PEX_UNC_ERR_SEV_FCP);
    eval 'sub PEX_UNC_ERR_SEV_CPL_TO () {0x4000;}' unless defined(&PEX_UNC_ERR_SEV_CPL_TO);
    eval 'sub PEX_UNC_ERR_SEV_CA () {0x8000;}' unless defined(&PEX_UNC_ERR_SEV_CA);
    eval 'sub PEX_UNC_ERR_SEV_UC () {0x10000;}' unless defined(&PEX_UNC_ERR_SEV_UC);
    eval 'sub PEX_UNC_ERR_SEV_ROV () {0x20000;}' unless defined(&PEX_UNC_ERR_SEV_ROV);
    eval 'sub PEX_UNC_ERR_SEV_MLFP () {0x40000;}' unless defined(&PEX_UNC_ERR_SEV_MLFP);
    eval 'sub PEX_UNC_ERR_SEV_ECRC () {0x80000;}' unless defined(&PEX_UNC_ERR_SEV_ECRC);
    eval 'sub PEX_UNC_ERR_SEV_UR () {0x100000;}' unless defined(&PEX_UNC_ERR_SEV_UR);
    eval 'sub ALC_TWSI_CFG () {0x218;}' unless defined(&ALC_TWSI_CFG);
    eval 'sub TWSI_CFG_SW_LD_START () {0x800;}' unless defined(&TWSI_CFG_SW_LD_START);
    eval 'sub TWSI_CFG_HW_LD_START () {0x1000;}' unless defined(&TWSI_CFG_HW_LD_START);
    eval 'sub TWSI_CFG_LD_EXIST () {0x400000;}' unless defined(&TWSI_CFG_LD_EXIST);
    eval 'sub ALC_PCIE_PHYMISC () {0x1000;}' unless defined(&ALC_PCIE_PHYMISC);
    eval 'sub PCIE_PHYMISC_FORCE_RCV_DET () {0x4;}' unless defined(&PCIE_PHYMISC_FORCE_RCV_DET);
    eval 'sub ALC_TWSI_DEBUG () {0x1108;}' unless defined(&ALC_TWSI_DEBUG);
    eval 'sub TWSI_DEBUG_DEV_EXIST () {0x20000000;}' unless defined(&TWSI_DEBUG_DEV_EXIST);
    eval 'sub ALC_EEPROM_CFG () {0x12c0;}' unless defined(&ALC_EEPROM_CFG);
    eval 'sub EEPROM_CFG_DATA_HI_MASK () {0xffff;}' unless defined(&EEPROM_CFG_DATA_HI_MASK);
    eval 'sub EEPROM_CFG_ADDR_MASK () {0x3ff0000;}' unless defined(&EEPROM_CFG_ADDR_MASK);
    eval 'sub EEPROM_CFG_ACK () {0x40000000;}' unless defined(&EEPROM_CFG_ACK);
    eval 'sub EEPROM_CFG_RW () {0x80000000;}' unless defined(&EEPROM_CFG_RW);
    eval 'sub EEPROM_CFG_DATA_HI_SHIFT () {0;}' unless defined(&EEPROM_CFG_DATA_HI_SHIFT);
    eval 'sub EEPROM_CFG_ADDR_SHIFT () {16;}' unless defined(&EEPROM_CFG_ADDR_SHIFT);
    eval 'sub ALC_EEPROM_DATA_LO () {0x12c4;}' unless defined(&ALC_EEPROM_DATA_LO);
    eval 'sub ALC_OPT_CFG () {0x12f0;}' unless defined(&ALC_OPT_CFG);
    eval 'sub OPT_CFG_CLK_ENB () {0x2;}' unless defined(&OPT_CFG_CLK_ENB);
    eval 'sub ALC_PM_CFG () {0x12f8;}' unless defined(&ALC_PM_CFG);
    eval 'sub PM_CFG_SERDES_ENB () {0x1;}' unless defined(&PM_CFG_SERDES_ENB);
    eval 'sub PM_CFG_RBER_ENB () {0x2;}' unless defined(&PM_CFG_RBER_ENB);
    eval 'sub PM_CFG_CLK_REQ_ENB () {0x4;}' unless defined(&PM_CFG_CLK_REQ_ENB);
    eval 'sub PM_CFG_ASPM_L1_ENB () {0x8;}' unless defined(&PM_CFG_ASPM_L1_ENB);
    eval 'sub PM_CFG_SERDES_L1_ENB () {0x10;}' unless defined(&PM_CFG_SERDES_L1_ENB);
    eval 'sub PM_CFG_SERDES_PLL_L1_ENB () {0x20;}' unless defined(&PM_CFG_SERDES_PLL_L1_ENB);
    eval 'sub PM_CFG_SERDES_PD_EX_L1 () {0x40;}' unless defined(&PM_CFG_SERDES_PD_EX_L1);
    eval 'sub PM_CFG_SERDES_BUDS_RX_L1_ENB () {0x80;}' unless defined(&PM_CFG_SERDES_BUDS_RX_L1_ENB);
    eval 'sub PM_CFG_L0S_ENTRY_TIMER_MASK () {0xf00;}' unless defined(&PM_CFG_L0S_ENTRY_TIMER_MASK);
    eval 'sub PM_CFG_ASPM_L0S_ENB () {0x1000;}' unless defined(&PM_CFG_ASPM_L0S_ENB);
    eval 'sub PM_CFG_CLK_SWH_L1 () {0x2000;}' unless defined(&PM_CFG_CLK_SWH_L1);
    eval 'sub PM_CFG_CLK_PWM_VER1_1 () {0x4000;}' unless defined(&PM_CFG_CLK_PWM_VER1_1);
    eval 'sub PM_CFG_PCIE_RECV () {0x8000;}' unless defined(&PM_CFG_PCIE_RECV);
    eval 'sub PM_CFG_L1_ENTRY_TIMER_MASK () {0xf0000;}' unless defined(&PM_CFG_L1_ENTRY_TIMER_MASK);
    eval 'sub PM_CFG_PM_REQ_TIMER_MASK () {0xf00000;}' unless defined(&PM_CFG_PM_REQ_TIMER_MASK);
    eval 'sub PM_CFG_LCKDET_TIMER_MASK () {0x3f000000;}' unless defined(&PM_CFG_LCKDET_TIMER_MASK);
    eval 'sub PM_CFG_MAC_ASPM_CHK () {0x40000000;}' unless defined(&PM_CFG_MAC_ASPM_CHK);
    eval 'sub PM_CFG_HOTRST () {0x80000000;}' unless defined(&PM_CFG_HOTRST);
    eval 'sub PM_CFG_L0S_ENTRY_TIMER_SHIFT () {8;}' unless defined(&PM_CFG_L0S_ENTRY_TIMER_SHIFT);
    eval 'sub PM_CFG_L1_ENTRY_TIMER_SHIFT () {16;}' unless defined(&PM_CFG_L1_ENTRY_TIMER_SHIFT);
    eval 'sub PM_CFG_PM_REQ_TIMER_SHIFT () {20;}' unless defined(&PM_CFG_PM_REQ_TIMER_SHIFT);
    eval 'sub PM_CFG_LCKDET_TIMER_SHIFT () {24;}' unless defined(&PM_CFG_LCKDET_TIMER_SHIFT);
    eval 'sub ALC_MASTER_CFG () {0x1400;}' unless defined(&ALC_MASTER_CFG);
    eval 'sub MASTER_RESET () {0x1;}' unless defined(&MASTER_RESET);
    eval 'sub MASTER_BERT_START () {0x10;}' unless defined(&MASTER_BERT_START);
    eval 'sub MASTER_TEST_MODE_MASK () {0xc0;}' unless defined(&MASTER_TEST_MODE_MASK);
    eval 'sub MASTER_MTIMER_ENB () {0x100;}' unless defined(&MASTER_MTIMER_ENB);
    eval 'sub MASTER_MANUAL_INTR_ENB () {0x200;}' unless defined(&MASTER_MANUAL_INTR_ENB);
    eval 'sub MASTER_IM_TX_TIMER_ENB () {0x400;}' unless defined(&MASTER_IM_TX_TIMER_ENB);
    eval 'sub MASTER_IM_RX_TIMER_ENB () {0x800;}' unless defined(&MASTER_IM_RX_TIMER_ENB);
    eval 'sub MASTER_CLK_SEL_DIS () {0x1000;}' unless defined(&MASTER_CLK_SEL_DIS);
    eval 'sub MASTER_CLK_SWH_MODE () {0x2000;}' unless defined(&MASTER_CLK_SWH_MODE);
    eval 'sub MASTER_INTR_RD_CLR () {0x4000;}' unless defined(&MASTER_INTR_RD_CLR);
    eval 'sub MASTER_CHIP_REV_MASK () {0xff0000;}' unless defined(&MASTER_CHIP_REV_MASK);
    eval 'sub MASTER_CHIP_ID_MASK () {0x7f000000;}' unless defined(&MASTER_CHIP_ID_MASK);
    eval 'sub MASTER_OTP_SEL () {0x80000000;}' unless defined(&MASTER_OTP_SEL);
    eval 'sub MASTER_TEST_MODE_SHIFT () {2;}' unless defined(&MASTER_TEST_MODE_SHIFT);
    eval 'sub MASTER_CHIP_REV_SHIFT () {16;}' unless defined(&MASTER_CHIP_REV_SHIFT);
    eval 'sub MASTER_CHIP_ID_SHIFT () {24;}' unless defined(&MASTER_CHIP_ID_SHIFT);
    eval 'sub ALC_TICK_USECS () {2;}' unless defined(&ALC_TICK_USECS);
    eval 'sub ALC_USECS {
        my($x) = @_;
	    eval q((($x) /  &ALC_TICK_USECS));
    }' unless defined(&ALC_USECS);
    eval 'sub ALC_MANUAL_TIMER () {0x1404;}' unless defined(&ALC_MANUAL_TIMER);
    eval 'sub ALC_IM_TIMER () {0x1408;}' unless defined(&ALC_IM_TIMER);
    eval 'sub IM_TIMER_TX_MASK () {0xffff;}' unless defined(&IM_TIMER_TX_MASK);
    eval 'sub IM_TIMER_RX_MASK () {0xffff0000;}' unless defined(&IM_TIMER_RX_MASK);
    eval 'sub IM_TIMER_TX_SHIFT () {0;}' unless defined(&IM_TIMER_TX_SHIFT);
    eval 'sub IM_TIMER_RX_SHIFT () {16;}' unless defined(&IM_TIMER_RX_SHIFT);
    eval 'sub ALC_IM_TIMER_MIN () {0;}' unless defined(&ALC_IM_TIMER_MIN);
    eval 'sub ALC_IM_TIMER_MAX () {130000;}' unless defined(&ALC_IM_TIMER_MAX);
    eval 'sub ALC_IM_RX_TIMER_DEFAULT () {100;}' unless defined(&ALC_IM_RX_TIMER_DEFAULT);
    eval 'sub ALC_IM_TX_TIMER_DEFAULT () {50000;}' unless defined(&ALC_IM_TX_TIMER_DEFAULT);
    eval 'sub ALC_GPHY_CFG () {0x140c;}' unless defined(&ALC_GPHY_CFG);
    eval 'sub GPHY_CFG_EXT_RESET () {0x1;}' unless defined(&GPHY_CFG_EXT_RESET);
    eval 'sub GPHY_CFG_RTL_MODE () {0x2;}' unless defined(&GPHY_CFG_RTL_MODE);
    eval 'sub GPHY_CFG_LED_MODE () {0x4;}' unless defined(&GPHY_CFG_LED_MODE);
    eval 'sub GPHY_CFG_ANEG_NOW () {0x8;}' unless defined(&GPHY_CFG_ANEG_NOW);
    eval 'sub GPHY_CFG_RECV_ANEG () {0x10;}' unless defined(&GPHY_CFG_RECV_ANEG);
    eval 'sub GPHY_CFG_GATE_25M_ENB () {0x20;}' unless defined(&GPHY_CFG_GATE_25M_ENB);
    eval 'sub GPHY_CFG_LPW_EXIT () {0x40;}' unless defined(&GPHY_CFG_LPW_EXIT);
    eval 'sub GPHY_CFG_PHY_IDDQ () {0x80;}' unless defined(&GPHY_CFG_PHY_IDDQ);
    eval 'sub GPHY_CFG_PHY_IDDQ_DIS () {0x100;}' unless defined(&GPHY_CFG_PHY_IDDQ_DIS);
    eval 'sub GPHY_CFG_PCLK_SEL_DIS () {0x200;}' unless defined(&GPHY_CFG_PCLK_SEL_DIS);
    eval 'sub GPHY_CFG_HIB_EN () {0x400;}' unless defined(&GPHY_CFG_HIB_EN);
    eval 'sub GPHY_CFG_HIB_PULSE () {0x800;}' unless defined(&GPHY_CFG_HIB_PULSE);
    eval 'sub GPHY_CFG_SEL_ANA_RESET () {0x1000;}' unless defined(&GPHY_CFG_SEL_ANA_RESET);
    eval 'sub GPHY_CFG_PHY_PLL_ON () {0x2000;}' unless defined(&GPHY_CFG_PHY_PLL_ON);
    eval 'sub GPHY_CFG_PWDOWN_HW () {0x4000;}' unless defined(&GPHY_CFG_PWDOWN_HW);
    eval 'sub GPHY_CFG_PHY_PLL_BYPASS () {0x8000;}' unless defined(&GPHY_CFG_PHY_PLL_BYPASS);
    eval 'sub ALC_IDLE_STATUS () {0x1410;}' unless defined(&ALC_IDLE_STATUS);
    eval 'sub IDLE_STATUS_RXMAC () {0x1;}' unless defined(&IDLE_STATUS_RXMAC);
    eval 'sub IDLE_STATUS_TXMAC () {0x2;}' unless defined(&IDLE_STATUS_TXMAC);
    eval 'sub IDLE_STATUS_RXQ () {0x4;}' unless defined(&IDLE_STATUS_RXQ);
    eval 'sub IDLE_STATUS_TXQ () {0x8;}' unless defined(&IDLE_STATUS_TXQ);
    eval 'sub IDLE_STATUS_DMARD () {0x10;}' unless defined(&IDLE_STATUS_DMARD);
    eval 'sub IDLE_STATUS_DMAWR () {0x20;}' unless defined(&IDLE_STATUS_DMAWR);
    eval 'sub IDLE_STATUS_SMB () {0x40;}' unless defined(&IDLE_STATUS_SMB);
    eval 'sub IDLE_STATUS_CMB () {0x80;}' unless defined(&IDLE_STATUS_CMB);
    eval 'sub ALC_MDIO () {0x1414;}' unless defined(&ALC_MDIO);
    eval 'sub MDIO_DATA_MASK () {0xffff;}' unless defined(&MDIO_DATA_MASK);
    eval 'sub MDIO_REG_ADDR_MASK () {0x1f0000;}' unless defined(&MDIO_REG_ADDR_MASK);
    eval 'sub MDIO_OP_READ () {0x200000;}' unless defined(&MDIO_OP_READ);
    eval 'sub MDIO_OP_WRITE () {0x;}' unless defined(&MDIO_OP_WRITE);
    eval 'sub MDIO_SUP_PREAMBLE () {0x400000;}' unless defined(&MDIO_SUP_PREAMBLE);
    eval 'sub MDIO_OP_EXECUTE () {0x800000;}' unless defined(&MDIO_OP_EXECUTE);
    eval 'sub MDIO_CLK_25_4 () {0x;}' unless defined(&MDIO_CLK_25_4);
    eval 'sub MDIO_CLK_25_6 () {0x2000000;}' unless defined(&MDIO_CLK_25_6);
    eval 'sub MDIO_CLK_25_8 () {0x3000000;}' unless defined(&MDIO_CLK_25_8);
    eval 'sub MDIO_CLK_25_10 () {0x4000000;}' unless defined(&MDIO_CLK_25_10);
    eval 'sub MDIO_CLK_25_14 () {0x5000000;}' unless defined(&MDIO_CLK_25_14);
    eval 'sub MDIO_CLK_25_20 () {0x6000000;}' unless defined(&MDIO_CLK_25_20);
    eval 'sub MDIO_CLK_25_28 () {0x7000000;}' unless defined(&MDIO_CLK_25_28);
    eval 'sub MDIO_OP_BUSY () {0x8000000;}' unless defined(&MDIO_OP_BUSY);
    eval 'sub MDIO_AP_ENB () {0x10000000;}' unless defined(&MDIO_AP_ENB);
    eval 'sub MDIO_DATA_SHIFT () {0;}' unless defined(&MDIO_DATA_SHIFT);
    eval 'sub MDIO_REG_ADDR_SHIFT () {16;}' unless defined(&MDIO_REG_ADDR_SHIFT);
    eval 'sub MDIO_REG_ADDR {
        my($x) = @_;
	    eval q(((($x) <<  &MDIO_REG_ADDR_SHIFT) &  &MDIO_REG_ADDR_MASK));
    }' unless defined(&MDIO_REG_ADDR);
    eval 'sub ALC_PHY_ADDR () {0;}' unless defined(&ALC_PHY_ADDR);
    eval 'sub ALC_PHY_STATUS () {0x1418;}' unless defined(&ALC_PHY_STATUS);
    eval 'sub PHY_STATUS_RECV_ENB () {0x1;}' unless defined(&PHY_STATUS_RECV_ENB);
    eval 'sub PHY_STATUS_GENERAL_MASK () {0xffff;}' unless defined(&PHY_STATUS_GENERAL_MASK);
    eval 'sub PHY_STATUS_OE_PWSP_MASK () {0x7ff0000;}' unless defined(&PHY_STATUS_OE_PWSP_MASK);
    eval 'sub PHY_STATUS_LPW_STATE () {0x80000000;}' unless defined(&PHY_STATUS_LPW_STATE);
    eval 'sub PHY_STATIS_OE_PWSP_SHIFT () {16;}' unless defined(&PHY_STATIS_OE_PWSP_SHIFT);
    eval 'sub ALC_BIST0 () {0x141c;}' unless defined(&ALC_BIST0);
    eval 'sub BIST0_ENB () {0x1;}' unless defined(&BIST0_ENB);
    eval 'sub BIST0_SRAM_FAIL () {0x2;}' unless defined(&BIST0_SRAM_FAIL);
    eval 'sub BIST0_FUSE_FLAG () {0x4;}' unless defined(&BIST0_FUSE_FLAG);
    eval 'sub ALC_BIST1 () {0x1420;}' unless defined(&ALC_BIST1);
    eval 'sub BIST1_ENB () {0x1;}' unless defined(&BIST1_ENB);
    eval 'sub BIST1_SRAM_FAIL () {0x2;}' unless defined(&BIST1_SRAM_FAIL);
    eval 'sub BIST1_FUSE_FLAG () {0x4;}' unless defined(&BIST1_FUSE_FLAG);
    eval 'sub ALC_SERDES_LOCK () {0x1424;}' unless defined(&ALC_SERDES_LOCK);
    eval 'sub SERDES_LOCK_DET () {0x1;}' unless defined(&SERDES_LOCK_DET);
    eval 'sub SERDES_LOCK_DET_ENB () {0x2;}' unless defined(&SERDES_LOCK_DET_ENB);
    eval 'sub ALC_MAC_CFG () {0x1480;}' unless defined(&ALC_MAC_CFG);
    eval 'sub MAC_CFG_TX_ENB () {0x1;}' unless defined(&MAC_CFG_TX_ENB);
    eval 'sub MAC_CFG_RX_ENB () {0x2;}' unless defined(&MAC_CFG_RX_ENB);
    eval 'sub MAC_CFG_TX_FC () {0x4;}' unless defined(&MAC_CFG_TX_FC);
    eval 'sub MAC_CFG_RX_FC () {0x8;}' unless defined(&MAC_CFG_RX_FC);
    eval 'sub MAC_CFG_LOOP () {0x10;}' unless defined(&MAC_CFG_LOOP);
    eval 'sub MAC_CFG_FULL_DUPLEX () {0x20;}' unless defined(&MAC_CFG_FULL_DUPLEX);
    eval 'sub MAC_CFG_TX_CRC_ENB () {0x40;}' unless defined(&MAC_CFG_TX_CRC_ENB);
    eval 'sub MAC_CFG_TX_AUTO_PAD () {0x80;}' unless defined(&MAC_CFG_TX_AUTO_PAD);
    eval 'sub MAC_CFG_TX_LENCHK () {0x100;}' unless defined(&MAC_CFG_TX_LENCHK);
    eval 'sub MAC_CFG_RX_JUMBO_ENB () {0x200;}' unless defined(&MAC_CFG_RX_JUMBO_ENB);
    eval 'sub MAC_CFG_PREAMBLE_MASK () {0x3c00;}' unless defined(&MAC_CFG_PREAMBLE_MASK);
    eval 'sub MAC_CFG_VLAN_TAG_STRIP () {0x4000;}' unless defined(&MAC_CFG_VLAN_TAG_STRIP);
    eval 'sub MAC_CFG_PROMISC () {0x8000;}' unless defined(&MAC_CFG_PROMISC);
    eval 'sub MAC_CFG_TX_PAUSE () {0x10000;}' unless defined(&MAC_CFG_TX_PAUSE);
    eval 'sub MAC_CFG_SCNT () {0x20000;}' unless defined(&MAC_CFG_SCNT);
    eval 'sub MAC_CFG_SYNC_RST_TX () {0x40000;}' unless defined(&MAC_CFG_SYNC_RST_TX);
    eval 'sub MAC_CFG_SIM_RST_TX () {0x80000;}' unless defined(&MAC_CFG_SIM_RST_TX);
    eval 'sub MAC_CFG_SPEED_MASK () {0x300000;}' unless defined(&MAC_CFG_SPEED_MASK);
    eval 'sub MAC_CFG_SPEED_10_100 () {0x100000;}' unless defined(&MAC_CFG_SPEED_10_100);
    eval 'sub MAC_CFG_SPEED_1000 () {0x200000;}' unless defined(&MAC_CFG_SPEED_1000);
    eval 'sub MAC_CFG_DBG_TX_BACKOFF () {0x400000;}' unless defined(&MAC_CFG_DBG_TX_BACKOFF);
    eval 'sub MAC_CFG_TX_JUMBO_ENB () {0x800000;}' unless defined(&MAC_CFG_TX_JUMBO_ENB);
    eval 'sub MAC_CFG_RXCSUM_ENB () {0x1000000;}' unless defined(&MAC_CFG_RXCSUM_ENB);
    eval 'sub MAC_CFG_ALLMULTI () {0x2000000;}' unless defined(&MAC_CFG_ALLMULTI);
    eval 'sub MAC_CFG_BCAST () {0x4000000;}' unless defined(&MAC_CFG_BCAST);
    eval 'sub MAC_CFG_DBG () {0x8000000;}' unless defined(&MAC_CFG_DBG);
    eval 'sub MAC_CFG_SINGLE_PAUSE_ENB () {0x10000000;}' unless defined(&MAC_CFG_SINGLE_PAUSE_ENB);
    eval 'sub MAC_CFG_PREAMBLE_SHIFT () {10;}' unless defined(&MAC_CFG_PREAMBLE_SHIFT);
    eval 'sub MAC_CFG_PREAMBLE_DEFAULT () {7;}' unless defined(&MAC_CFG_PREAMBLE_DEFAULT);
    eval 'sub ALC_IPG_IFG_CFG () {0x1484;}' unless defined(&ALC_IPG_IFG_CFG);
    eval 'sub IPG_IFG_IPGT_MASK () {0x7f;}' unless defined(&IPG_IFG_IPGT_MASK);
    eval 'sub IPG_IFG_MIFG_MASK () {0xff00;}' unless defined(&IPG_IFG_MIFG_MASK);
    eval 'sub IPG_IFG_IPG1_MASK () {0x7f0000;}' unless defined(&IPG_IFG_IPG1_MASK);
    eval 'sub IPG_IFG_IPG2_MASK () {0x7f000000;}' unless defined(&IPG_IFG_IPG2_MASK);
    eval 'sub IPG_IFG_IPGT_SHIFT () {0;}' unless defined(&IPG_IFG_IPGT_SHIFT);
    eval 'sub IPG_IFG_IPGT_DEFAULT () {0x60;}' unless defined(&IPG_IFG_IPGT_DEFAULT);
    eval 'sub IPG_IFG_MIFG_SHIFT () {8;}' unless defined(&IPG_IFG_MIFG_SHIFT);
    eval 'sub IPG_IFG_MIFG_DEFAULT () {0x50;}' unless defined(&IPG_IFG_MIFG_DEFAULT);
    eval 'sub IPG_IFG_IPG1_SHIFT () {16;}' unless defined(&IPG_IFG_IPG1_SHIFT);
    eval 'sub IPG_IFG_IPG1_DEFAULT () {0x40;}' unless defined(&IPG_IFG_IPG1_DEFAULT);
    eval 'sub IPG_IFG_IPG2_SHIFT () {24;}' unless defined(&IPG_IFG_IPG2_SHIFT);
    eval 'sub IPG_IFG_IPG2_DEFAULT () {0x60;}' unless defined(&IPG_IFG_IPG2_DEFAULT);
    eval 'sub ALC_PAR0 () {0x1488;}' unless defined(&ALC_PAR0);
    eval 'sub ALC_PAR1 () {0x148c;}' unless defined(&ALC_PAR1);
    eval 'sub ALC_MAR0 () {0x1490;}' unless defined(&ALC_MAR0);
    eval 'sub ALC_MAR1 () {0x1494;}' unless defined(&ALC_MAR1);
    eval 'sub ALC_HDPX_CFG () {0x1498;}' unless defined(&ALC_HDPX_CFG);
    eval 'sub HDPX_CFG_LCOL_MASK () {0x3ff;}' unless defined(&HDPX_CFG_LCOL_MASK);
    eval 'sub HDPX_CFG_RETRY_MASK () {0xf000;}' unless defined(&HDPX_CFG_RETRY_MASK);
    eval 'sub HDPX_CFG_EXC_DEF_EN () {0x10000;}' unless defined(&HDPX_CFG_EXC_DEF_EN);
    eval 'sub HDPX_CFG_NO_BACK_C () {0x20000;}' unless defined(&HDPX_CFG_NO_BACK_C);
    eval 'sub HDPX_CFG_NO_BACK_P () {0x40000;}' unless defined(&HDPX_CFG_NO_BACK_P);
    eval 'sub HDPX_CFG_ABEBE () {0x80000;}' unless defined(&HDPX_CFG_ABEBE);
    eval 'sub HDPX_CFG_ABEBT_MASK () {0xf00000;}' unless defined(&HDPX_CFG_ABEBT_MASK);
    eval 'sub HDPX_CFG_JAMIPG_MASK () {0xf000000;}' unless defined(&HDPX_CFG_JAMIPG_MASK);
    eval 'sub HDPX_CFG_LCOL_SHIFT () {0;}' unless defined(&HDPX_CFG_LCOL_SHIFT);
    eval 'sub HDPX_CFG_LCOL_DEFAULT () {0x37;}' unless defined(&HDPX_CFG_LCOL_DEFAULT);
    eval 'sub HDPX_CFG_RETRY_SHIFT () {12;}' unless defined(&HDPX_CFG_RETRY_SHIFT);
    eval 'sub HDPX_CFG_RETRY_DEFAULT () {0xf;}' unless defined(&HDPX_CFG_RETRY_DEFAULT);
    eval 'sub HDPX_CFG_ABEBT_SHIFT () {20;}' unless defined(&HDPX_CFG_ABEBT_SHIFT);
    eval 'sub HDPX_CFG_ABEBT_DEFAULT () {0xa;}' unless defined(&HDPX_CFG_ABEBT_DEFAULT);
    eval 'sub HDPX_CFG_JAMIPG_SHIFT () {24;}' unless defined(&HDPX_CFG_JAMIPG_SHIFT);
    eval 'sub HDPX_CFG_JAMIPG_DEFAULT () {0x7;}' unless defined(&HDPX_CFG_JAMIPG_DEFAULT);
    eval 'sub ALC_FRAME_SIZE () {0x149c;}' unless defined(&ALC_FRAME_SIZE);
    eval 'sub ALC_WOL_CFG () {0x14a0;}' unless defined(&ALC_WOL_CFG);
    eval 'sub WOL_CFG_PATTERN () {0x1;}' unless defined(&WOL_CFG_PATTERN);
    eval 'sub WOL_CFG_PATTERN_ENB () {0x2;}' unless defined(&WOL_CFG_PATTERN_ENB);
    eval 'sub WOL_CFG_MAGIC () {0x4;}' unless defined(&WOL_CFG_MAGIC);
    eval 'sub WOL_CFG_MAGIC_ENB () {0x8;}' unless defined(&WOL_CFG_MAGIC_ENB);
    eval 'sub WOL_CFG_LINK_CHG () {0x10;}' unless defined(&WOL_CFG_LINK_CHG);
    eval 'sub WOL_CFG_LINK_CHG_ENB () {0x20;}' unless defined(&WOL_CFG_LINK_CHG_ENB);
    eval 'sub WOL_CFG_PATTERN_DET () {0x100;}' unless defined(&WOL_CFG_PATTERN_DET);
    eval 'sub WOL_CFG_MAGIC_DET () {0x200;}' unless defined(&WOL_CFG_MAGIC_DET);
    eval 'sub WOL_CFG_LINK_CHG_DET () {0x400;}' unless defined(&WOL_CFG_LINK_CHG_DET);
    eval 'sub WOL_CFG_CLK_SWITCH_ENB () {0x8000;}' unless defined(&WOL_CFG_CLK_SWITCH_ENB);
    eval 'sub WOL_CFG_PATTERN0 () {0x10000;}' unless defined(&WOL_CFG_PATTERN0);
    eval 'sub WOL_CFG_PATTERN1 () {0x20000;}' unless defined(&WOL_CFG_PATTERN1);
    eval 'sub WOL_CFG_PATTERN2 () {0x40000;}' unless defined(&WOL_CFG_PATTERN2);
    eval 'sub WOL_CFG_PATTERN3 () {0x80000;}' unless defined(&WOL_CFG_PATTERN3);
    eval 'sub WOL_CFG_PATTERN4 () {0x100000;}' unless defined(&WOL_CFG_PATTERN4);
    eval 'sub WOL_CFG_PATTERN5 () {0x200000;}' unless defined(&WOL_CFG_PATTERN5);
    eval 'sub WOL_CFG_PATTERN6 () {0x400000;}' unless defined(&WOL_CFG_PATTERN6);
    eval 'sub ALC_PATTERN_CFG0 () {0x14a4;}' unless defined(&ALC_PATTERN_CFG0);
    eval 'sub PATTERN_CFG_0_LEN_MASK () {0x7f;}' unless defined(&PATTERN_CFG_0_LEN_MASK);
    eval 'sub PATTERN_CFG_1_LEN_MASK () {0x7f00;}' unless defined(&PATTERN_CFG_1_LEN_MASK);
    eval 'sub PATTERN_CFG_2_LEN_MASK () {0x7f0000;}' unless defined(&PATTERN_CFG_2_LEN_MASK);
    eval 'sub PATTERN_CFG_3_LEN_MASK () {0x7f000000;}' unless defined(&PATTERN_CFG_3_LEN_MASK);
    eval 'sub ALC_PATTERN_CFG1 () {0x14a8;}' unless defined(&ALC_PATTERN_CFG1);
    eval 'sub PATTERN_CFG_4_LEN_MASK () {0x7f;}' unless defined(&PATTERN_CFG_4_LEN_MASK);
    eval 'sub PATTERN_CFG_5_LEN_MASK () {0x7f00;}' unless defined(&PATTERN_CFG_5_LEN_MASK);
    eval 'sub PATTERN_CFG_6_LEN_MASK () {0x7f0000;}' unless defined(&PATTERN_CFG_6_LEN_MASK);
    eval 'sub ALC_RSS_KEY0 () {0x14b0;}' unless defined(&ALC_RSS_KEY0);
    eval 'sub ALC_RSS_KEY1 () {0x14b4;}' unless defined(&ALC_RSS_KEY1);
    eval 'sub ALC_RSS_KEY2 () {0x14b8;}' unless defined(&ALC_RSS_KEY2);
    eval 'sub ALC_RSS_KEY3 () {0x14bc;}' unless defined(&ALC_RSS_KEY3);
    eval 'sub ALC_RSS_KEY4 () {0x14c0;}' unless defined(&ALC_RSS_KEY4);
    eval 'sub ALC_RSS_KEY5 () {0x14c4;}' unless defined(&ALC_RSS_KEY5);
    eval 'sub ALC_RSS_KEY6 () {0x14c8;}' unless defined(&ALC_RSS_KEY6);
    eval 'sub ALC_RSS_KEY7 () {0x14cc;}' unless defined(&ALC_RSS_KEY7);
    eval 'sub ALC_RSS_KEY8 () {0x14d0;}' unless defined(&ALC_RSS_KEY8);
    eval 'sub ALC_RSS_KEY9 () {0x14d4;}' unless defined(&ALC_RSS_KEY9);
    eval 'sub ALC_RSS_IDT_TABLE0 () {0x14e0;}' unless defined(&ALC_RSS_IDT_TABLE0);
    eval 'sub ALC_RSS_IDT_TABLE1 () {0x14e4;}' unless defined(&ALC_RSS_IDT_TABLE1);
    eval 'sub ALC_RSS_IDT_TABLE2 () {0x14e8;}' unless defined(&ALC_RSS_IDT_TABLE2);
    eval 'sub ALC_RSS_IDT_TABLE3 () {0x14ec;}' unless defined(&ALC_RSS_IDT_TABLE3);
    eval 'sub ALC_RSS_IDT_TABLE4 () {0x14f0;}' unless defined(&ALC_RSS_IDT_TABLE4);
    eval 'sub ALC_RSS_IDT_TABLE5 () {0x14f4;}' unless defined(&ALC_RSS_IDT_TABLE5);
    eval 'sub ALC_RSS_IDT_TABLE6 () {0x14f8;}' unless defined(&ALC_RSS_IDT_TABLE6);
    eval 'sub ALC_RSS_IDT_TABLE7 () {0x14fc;}' unless defined(&ALC_RSS_IDT_TABLE7);
    eval 'sub ALC_SRAM_RD0_ADDR () {0x1500;}' unless defined(&ALC_SRAM_RD0_ADDR);
    eval 'sub ALC_SRAM_RD1_ADDR () {0x1504;}' unless defined(&ALC_SRAM_RD1_ADDR);
    eval 'sub ALC_SRAM_RD2_ADDR () {0x1508;}' unless defined(&ALC_SRAM_RD2_ADDR);
    eval 'sub ALC_SRAM_RD3_ADDR () {0x150c;}' unless defined(&ALC_SRAM_RD3_ADDR);
    eval 'sub RD_HEAD_ADDR_MASK () {0x3ff;}' unless defined(&RD_HEAD_ADDR_MASK);
    eval 'sub RD_TAIL_ADDR_MASK () {0x3ff0000;}' unless defined(&RD_TAIL_ADDR_MASK);
    eval 'sub RD_HEAD_ADDR_SHIFT () {0;}' unless defined(&RD_HEAD_ADDR_SHIFT);
    eval 'sub RD_TAIL_ADDR_SHIFT () {16;}' unless defined(&RD_TAIL_ADDR_SHIFT);
    eval 'sub ALC_RD_NIC_LEN0 () {0x1510;}' unless defined(&ALC_RD_NIC_LEN0);
    eval 'sub RD_NIC_LEN_MASK () {0x3ff;}' unless defined(&RD_NIC_LEN_MASK);
    eval 'sub ALC_RD_NIC_LEN1 () {0x1514;}' unless defined(&ALC_RD_NIC_LEN1);
    eval 'sub ALC_SRAM_TD_ADDR () {0x1518;}' unless defined(&ALC_SRAM_TD_ADDR);
    eval 'sub TD_HEAD_ADDR_MASK () {0x3ff;}' unless defined(&TD_HEAD_ADDR_MASK);
    eval 'sub TD_TAIL_ADDR_MASK () {0x3ff0000;}' unless defined(&TD_TAIL_ADDR_MASK);
    eval 'sub TD_HEAD_ADDR_SHIFT () {0;}' unless defined(&TD_HEAD_ADDR_SHIFT);
    eval 'sub TD_TAIL_ADDR_SHIFT () {16;}' unless defined(&TD_TAIL_ADDR_SHIFT);
    eval 'sub ALC_SRAM_TD_LEN () {0x151c;}' unless defined(&ALC_SRAM_TD_LEN);
    eval 'sub SRAM_TD_LEN_MASK () {0x3ff;}' unless defined(&SRAM_TD_LEN_MASK);
    eval 'sub ALC_SRAM_RX_FIFO_ADDR () {0x1520;}' unless defined(&ALC_SRAM_RX_FIFO_ADDR);
    eval 'sub ALC_SRAM_RX_FIFO_LEN () {0x1524;}' unless defined(&ALC_SRAM_RX_FIFO_LEN);
    eval 'sub ALC_SRAM_TX_FIFO_ADDR () {0x1528;}' unless defined(&ALC_SRAM_TX_FIFO_ADDR);
    eval 'sub ALC_SRAM_TX_FIFO_LEN () {0x152c;}' unless defined(&ALC_SRAM_TX_FIFO_LEN);
    eval 'sub ALC_SRAM_TCPH_ADDR () {0x1530;}' unless defined(&ALC_SRAM_TCPH_ADDR);
    eval 'sub SRAM_TCPH_ADDR_MASK () {0xfff;}' unless defined(&SRAM_TCPH_ADDR_MASK);
    eval 'sub SRAM_PATH_ADDR_MASK () {0xfff0000;}' unless defined(&SRAM_PATH_ADDR_MASK);
    eval 'sub SRAM_TCPH_ADDR_SHIFT () {0;}' unless defined(&SRAM_TCPH_ADDR_SHIFT);
    eval 'sub SRAM_PKTH_ADDR_SHIFT () {16;}' unless defined(&SRAM_PKTH_ADDR_SHIFT);
    eval 'sub ALC_DMA_BLOCK () {0x1534;}' unless defined(&ALC_DMA_BLOCK);
    eval 'sub DMA_BLOCK_LOAD () {0x1;}' unless defined(&DMA_BLOCK_LOAD);
    eval 'sub ALC_RX_BASE_ADDR_HI () {0x1540;}' unless defined(&ALC_RX_BASE_ADDR_HI);
    eval 'sub ALC_TX_BASE_ADDR_HI () {0x1544;}' unless defined(&ALC_TX_BASE_ADDR_HI);
    eval 'sub ALC_SMB_BASE_ADDR_HI () {0x1548;}' unless defined(&ALC_SMB_BASE_ADDR_HI);
    eval 'sub ALC_SMB_BASE_ADDR_LO () {0x154c;}' unless defined(&ALC_SMB_BASE_ADDR_LO);
    eval 'sub ALC_RD0_HEAD_ADDR_LO () {0x1550;}' unless defined(&ALC_RD0_HEAD_ADDR_LO);
    eval 'sub ALC_RD1_HEAD_ADDR_LO () {0x1554;}' unless defined(&ALC_RD1_HEAD_ADDR_LO);
    eval 'sub ALC_RD2_HEAD_ADDR_LO () {0x1558;}' unless defined(&ALC_RD2_HEAD_ADDR_LO);
    eval 'sub ALC_RD3_HEAD_ADDR_LO () {0x155c;}' unless defined(&ALC_RD3_HEAD_ADDR_LO);
    eval 'sub ALC_RD_RING_CNT () {0x1560;}' unless defined(&ALC_RD_RING_CNT);
    eval 'sub RD_RING_CNT_MASK () {0xfff;}' unless defined(&RD_RING_CNT_MASK);
    eval 'sub RD_RING_CNT_SHIFT () {0;}' unless defined(&RD_RING_CNT_SHIFT);
    eval 'sub ALC_RX_BUF_SIZE () {0x1564;}' unless defined(&ALC_RX_BUF_SIZE);
    eval 'sub RX_BUF_SIZE_MASK () {0xffff;}' unless defined(&RX_BUF_SIZE_MASK);
    eval 'sub RX_BUF_SIZE_MAX () {1536;}' unless defined(&RX_BUF_SIZE_MAX);
    eval 'sub ALC_RRD0_HEAD_ADDR_LO () {0x1568;}' unless defined(&ALC_RRD0_HEAD_ADDR_LO);
    eval 'sub ALC_RRD1_HEAD_ADDR_LO () {0x156c;}' unless defined(&ALC_RRD1_HEAD_ADDR_LO);
    eval 'sub ALC_RRD2_HEAD_ADDR_LO () {0x1570;}' unless defined(&ALC_RRD2_HEAD_ADDR_LO);
    eval 'sub ALC_RRD3_HEAD_ADDR_LO () {0x1574;}' unless defined(&ALC_RRD3_HEAD_ADDR_LO);
    eval 'sub ALC_RRD_RING_CNT () {0x1578;}' unless defined(&ALC_RRD_RING_CNT);
    eval 'sub RRD_RING_CNT_MASK () {0xfff;}' unless defined(&RRD_RING_CNT_MASK);
    eval 'sub RRD_RING_CNT_SHIFT () {0;}' unless defined(&RRD_RING_CNT_SHIFT);
    eval 'sub ALC_TDH_HEAD_ADDR_LO () {0x157c;}' unless defined(&ALC_TDH_HEAD_ADDR_LO);
    eval 'sub ALC_TDL_HEAD_ADDR_LO () {0x1580;}' unless defined(&ALC_TDL_HEAD_ADDR_LO);
    eval 'sub ALC_TD_RING_CNT () {0x1584;}' unless defined(&ALC_TD_RING_CNT);
    eval 'sub TD_RING_CNT_MASK () {0xffff;}' unless defined(&TD_RING_CNT_MASK);
    eval 'sub TD_RING_CNT_SHIFT () {0;}' unless defined(&TD_RING_CNT_SHIFT);
    eval 'sub ALC_CMB_BASE_ADDR_LO () {0x1588;}' unless defined(&ALC_CMB_BASE_ADDR_LO);
    eval 'sub ALC_TXQ_CFG () {0x1590;}' unless defined(&ALC_TXQ_CFG);
    eval 'sub TXQ_CFG_TD_BURST_MASK () {0xf;}' unless defined(&TXQ_CFG_TD_BURST_MASK);
    eval 'sub TXQ_CFG_IP_OPTION_ENB () {0x10;}' unless defined(&TXQ_CFG_IP_OPTION_ENB);
    eval 'sub TXQ_CFG_ENB () {0x20;}' unless defined(&TXQ_CFG_ENB);
    eval 'sub TXQ_CFG_ENHANCED_MODE () {0x40;}' unless defined(&TXQ_CFG_ENHANCED_MODE);
    eval 'sub TXQ_CFG_8023_ENB () {0x80;}' unless defined(&TXQ_CFG_8023_ENB);
    eval 'sub TXQ_CFG_TX_FIFO_BURST_MASK () {0xffff0000;}' unless defined(&TXQ_CFG_TX_FIFO_BURST_MASK);
    eval 'sub TXQ_CFG_TD_BURST_SHIFT () {0;}' unless defined(&TXQ_CFG_TD_BURST_SHIFT);
    eval 'sub TXQ_CFG_TD_BURST_DEFAULT () {5;}' unless defined(&TXQ_CFG_TD_BURST_DEFAULT);
    eval 'sub TXQ_CFG_TX_FIFO_BURST_SHIFT () {16;}' unless defined(&TXQ_CFG_TX_FIFO_BURST_SHIFT);
    eval 'sub ALC_TSO_OFFLOAD_THRESH () {0x1594;}' unless defined(&ALC_TSO_OFFLOAD_THRESH);
    eval 'sub TSO_OFFLOAD_THRESH_MASK () {0x7ff;}' unless defined(&TSO_OFFLOAD_THRESH_MASK);
    eval 'sub TSO_OFFLOAD_THRESH_SHIFT () {0;}' unless defined(&TSO_OFFLOAD_THRESH_SHIFT);
    eval 'sub TSO_OFFLOAD_THRESH_UNIT () {8;}' unless defined(&TSO_OFFLOAD_THRESH_UNIT);
    eval 'sub TSO_OFFLOAD_THRESH_UNIT_SHIFT () {3;}' unless defined(&TSO_OFFLOAD_THRESH_UNIT_SHIFT);
    eval 'sub ALC_TXF_WATER_MARK () {0x1598;}' unless defined(&ALC_TXF_WATER_MARK);
    eval 'sub TXF_WATER_MARK_HI_MASK () {0xfff;}' unless defined(&TXF_WATER_MARK_HI_MASK);
    eval 'sub TXF_WATER_MARK_LO_MASK () {0xfff0000;}' unless defined(&TXF_WATER_MARK_LO_MASK);
    eval 'sub TXF_WATER_MARK_BURST_ENB () {0x80000000;}' unless defined(&TXF_WATER_MARK_BURST_ENB);
    eval 'sub TXF_WATER_MARK_LO_SHIFT () {0;}' unless defined(&TXF_WATER_MARK_LO_SHIFT);
    eval 'sub TXF_WATER_MARK_HI_SHIFT () {16;}' unless defined(&TXF_WATER_MARK_HI_SHIFT);
    eval 'sub ALC_THROUGHPUT_MON () {0x159c;}' unless defined(&ALC_THROUGHPUT_MON);
    eval 'sub THROUGHPUT_MON_RATE_MASK () {0x3;}' unless defined(&THROUGHPUT_MON_RATE_MASK);
    eval 'sub THROUGHPUT_MON_ENB () {0x80;}' unless defined(&THROUGHPUT_MON_ENB);
    eval 'sub THROUGHPUT_MON_RATE_SHIFT () {0;}' unless defined(&THROUGHPUT_MON_RATE_SHIFT);
    eval 'sub ALC_RXQ_CFG () {0x15a0;}' unless defined(&ALC_RXQ_CFG);
    eval 'sub RXQ_CFG_ASPM_THROUGHPUT_LIMIT_MASK () {0x3;}' unless defined(&RXQ_CFG_ASPM_THROUGHPUT_LIMIT_MASK);
    eval 'sub RXQ_CFG_ASPM_THROUGHPUT_LIMIT_NONE () {0x;}' unless defined(&RXQ_CFG_ASPM_THROUGHPUT_LIMIT_NONE);
    eval 'sub RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M () {0x1;}' unless defined(&RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M);
    eval 'sub RXQ_CFG_ASPM_THROUGHPUT_LIMIT_10M () {0x2;}' unless defined(&RXQ_CFG_ASPM_THROUGHPUT_LIMIT_10M);
    eval 'sub RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M () {0x3;}' unless defined(&RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M);
    eval 'sub RXQ_CFG_QUEUE1_ENB () {0x10;}' unless defined(&RXQ_CFG_QUEUE1_ENB);
    eval 'sub RXQ_CFG_QUEUE2_ENB () {0x20;}' unless defined(&RXQ_CFG_QUEUE2_ENB);
    eval 'sub RXQ_CFG_QUEUE3_ENB () {0x40;}' unless defined(&RXQ_CFG_QUEUE3_ENB);
    eval 'sub RXQ_CFG_IPV6_CSUM_ENB () {0x80;}' unless defined(&RXQ_CFG_IPV6_CSUM_ENB);
    eval 'sub RXQ_CFG_RSS_HASH_TBL_LEN_MASK () {0xff00;}' unless defined(&RXQ_CFG_RSS_HASH_TBL_LEN_MASK);
    eval 'sub RXQ_CFG_RSS_HASH_IPV4 () {0x10000;}' unless defined(&RXQ_CFG_RSS_HASH_IPV4);
    eval 'sub RXQ_CFG_RSS_HASH_IPV4_TCP () {0x20000;}' unless defined(&RXQ_CFG_RSS_HASH_IPV4_TCP);
    eval 'sub RXQ_CFG_RSS_HASH_IPV6 () {0x40000;}' unless defined(&RXQ_CFG_RSS_HASH_IPV6);
    eval 'sub RXQ_CFG_RSS_HASH_IPV6_TCP () {0x80000;}' unless defined(&RXQ_CFG_RSS_HASH_IPV6_TCP);
    eval 'sub RXQ_CFG_RD_BURST_MASK () {0x3f00000;}' unless defined(&RXQ_CFG_RD_BURST_MASK);
    eval 'sub RXQ_CFG_RSS_MODE_DIS () {0x;}' unless defined(&RXQ_CFG_RSS_MODE_DIS);
    eval 'sub RXQ_CFG_RSS_MODE_SQSINT () {0x4000000;}' unless defined(&RXQ_CFG_RSS_MODE_SQSINT);
    eval 'sub RXQ_CFG_RSS_MODE_MQUESINT () {0x8000000;}' unless defined(&RXQ_CFG_RSS_MODE_MQUESINT);
    eval 'sub RXQ_CFG_RSS_MODE_MQUEMINT () {0xc000000;}' unless defined(&RXQ_CFG_RSS_MODE_MQUEMINT);
    eval 'sub RXQ_CFG_NIP_QUEUE_SEL_TBL () {0x10000000;}' unless defined(&RXQ_CFG_NIP_QUEUE_SEL_TBL);
    eval 'sub RXQ_CFG_RSS_HASH_ENB () {0x20000000;}' unless defined(&RXQ_CFG_RSS_HASH_ENB);
    eval 'sub RXQ_CFG_CUT_THROUGH_ENB () {0x40000000;}' unless defined(&RXQ_CFG_CUT_THROUGH_ENB);
    eval 'sub RXQ_CFG_QUEUE0_ENB () {0x80000000;}' unless defined(&RXQ_CFG_QUEUE0_ENB);
    eval 'sub RXQ_CFG_RSS_HASH_TBL_LEN_SHIFT () {8;}' unless defined(&RXQ_CFG_RSS_HASH_TBL_LEN_SHIFT);
    eval 'sub RXQ_CFG_RD_BURST_DEFAULT () {8;}' unless defined(&RXQ_CFG_RD_BURST_DEFAULT);
    eval 'sub RXQ_CFG_RD_BURST_SHIFT () {20;}' unless defined(&RXQ_CFG_RD_BURST_SHIFT);
    eval 'sub RXQ_CFG_ENB () {( &RXQ_CFG_QUEUE0_ENB |  &RXQ_CFG_QUEUE1_ENB |  &RXQ_CFG_QUEUE2_ENB |  &RXQ_CFG_QUEUE3_ENB);}' unless defined(&RXQ_CFG_ENB);
    eval 'sub ALC_RX_RD_FREE_THRESH () {0x15a4;}' unless defined(&ALC_RX_RD_FREE_THRESH);
    eval 'sub RX_RD_FREE_THRESH_HI_MASK () {0x3f;}' unless defined(&RX_RD_FREE_THRESH_HI_MASK);
    eval 'sub RX_RD_FREE_THRESH_LO_MASK () {0xfc0;}' unless defined(&RX_RD_FREE_THRESH_LO_MASK);
    eval 'sub RX_RD_FREE_THRESH_HI_SHIFT () {0;}' unless defined(&RX_RD_FREE_THRESH_HI_SHIFT);
    eval 'sub RX_RD_FREE_THRESH_LO_SHIFT () {6;}' unless defined(&RX_RD_FREE_THRESH_LO_SHIFT);
    eval 'sub RX_RD_FREE_THRESH_HI_DEFAULT () {16;}' unless defined(&RX_RD_FREE_THRESH_HI_DEFAULT);
    eval 'sub RX_RD_FREE_THRESH_LO_DEFAULT () {8;}' unless defined(&RX_RD_FREE_THRESH_LO_DEFAULT);
    eval 'sub ALC_RX_FIFO_PAUSE_THRESH () {0x15a8;}' unless defined(&ALC_RX_FIFO_PAUSE_THRESH);
    eval 'sub RX_FIFO_PAUSE_THRESH_LO_MASK () {0xfff;}' unless defined(&RX_FIFO_PAUSE_THRESH_LO_MASK);
    eval 'sub RX_FIFO_PAUSE_THRESH_HI_MASK () {0xfff0000;}' unless defined(&RX_FIFO_PAUSE_THRESH_HI_MASK);
    eval 'sub RX_FIFO_PAUSE_THRESH_LO_SHIFT () {0;}' unless defined(&RX_FIFO_PAUSE_THRESH_LO_SHIFT);
    eval 'sub RX_FIFO_PAUSE_THRESH_HI_SHIFT () {16;}' unless defined(&RX_FIFO_PAUSE_THRESH_HI_SHIFT);
    eval 'sub ALC_RD_DMA_CFG () {0x15ac;}' unless defined(&ALC_RD_DMA_CFG);
    eval 'sub RD_DMA_CFG_THRESH_MASK () {0xfff;}' unless defined(&RD_DMA_CFG_THRESH_MASK);
    eval 'sub RD_DMA_CFG_TIMER_MASK () {0xffff0000;}' unless defined(&RD_DMA_CFG_TIMER_MASK);
    eval 'sub RD_DMA_CFG_THRESH_SHIFT () {0;}' unless defined(&RD_DMA_CFG_THRESH_SHIFT);
    eval 'sub RD_DMA_CFG_TIMER_SHIFT () {16;}' unless defined(&RD_DMA_CFG_TIMER_SHIFT);
    eval 'sub RD_DMA_CFG_THRESH_DEFAULT () {0x100;}' unless defined(&RD_DMA_CFG_THRESH_DEFAULT);
    eval 'sub RD_DMA_CFG_TIMER_DEFAULT () {0;}' unless defined(&RD_DMA_CFG_TIMER_DEFAULT);
    eval 'sub RD_DMA_CFG_TICK_USECS () {8;}' unless defined(&RD_DMA_CFG_TICK_USECS);
    eval 'sub ALC_RD_DMA_CFG_USECS {
        my($x) = @_;
	    eval q((($x) /  &RD_DMA_CFG_TICK_USECS));
    }' unless defined(&ALC_RD_DMA_CFG_USECS);
    eval 'sub ALC_RSS_HASH_VALUE () {0x15b0;}' unless defined(&ALC_RSS_HASH_VALUE);
    eval 'sub ALC_RSS_HASH_FLAG () {0x15b4;}' unless defined(&ALC_RSS_HASH_FLAG);
    eval 'sub ALC_RSS_CPU () {0x15b8;}' unless defined(&ALC_RSS_CPU);
    eval 'sub ALC_DMA_CFG () {0x15c0;}' unless defined(&ALC_DMA_CFG);
    eval 'sub DMA_CFG_IN_ORDER () {0x1;}' unless defined(&DMA_CFG_IN_ORDER);
    eval 'sub DMA_CFG_ENH_ORDER () {0x2;}' unless defined(&DMA_CFG_ENH_ORDER);
    eval 'sub DMA_CFG_OUT_ORDER () {0x4;}' unless defined(&DMA_CFG_OUT_ORDER);
    eval 'sub DMA_CFG_RCB_64 () {0x;}' unless defined(&DMA_CFG_RCB_64);
    eval 'sub DMA_CFG_RCB_128 () {0x8;}' unless defined(&DMA_CFG_RCB_128);
    eval 'sub DMA_CFG_RD_BURST_128 () {0x;}' unless defined(&DMA_CFG_RD_BURST_128);
    eval 'sub DMA_CFG_RD_BURST_256 () {0x10;}' unless defined(&DMA_CFG_RD_BURST_256);
    eval 'sub DMA_CFG_RD_BURST_512 () {0x20;}' unless defined(&DMA_CFG_RD_BURST_512);
    eval 'sub DMA_CFG_RD_BURST_1024 () {0x30;}' unless defined(&DMA_CFG_RD_BURST_1024);
    eval 'sub DMA_CFG_RD_BURST_2048 () {0x40;}' unless defined(&DMA_CFG_RD_BURST_2048);
    eval 'sub DMA_CFG_RD_BURST_4096 () {0x50;}' unless defined(&DMA_CFG_RD_BURST_4096);
    eval 'sub DMA_CFG_WR_BURST_128 () {0x;}' unless defined(&DMA_CFG_WR_BURST_128);
    eval 'sub DMA_CFG_WR_BURST_256 () {0x80;}' unless defined(&DMA_CFG_WR_BURST_256);
    eval 'sub DMA_CFG_WR_BURST_512 () {0x100;}' unless defined(&DMA_CFG_WR_BURST_512);
    eval 'sub DMA_CFG_WR_BURST_1024 () {0x180;}' unless defined(&DMA_CFG_WR_BURST_1024);
    eval 'sub DMA_CFG_WR_BURST_2048 () {0x200;}' unless defined(&DMA_CFG_WR_BURST_2048);
    eval 'sub DMA_CFG_WR_BURST_4096 () {0x280;}' unless defined(&DMA_CFG_WR_BURST_4096);
    eval 'sub DMA_CFG_RD_REQ_PRI () {0x400;}' unless defined(&DMA_CFG_RD_REQ_PRI);
    eval 'sub DMA_CFG_RD_DELAY_CNT_MASK () {0xf800;}' unless defined(&DMA_CFG_RD_DELAY_CNT_MASK);
    eval 'sub DMA_CFG_WR_DELAY_CNT_MASK () {0xf0000;}' unless defined(&DMA_CFG_WR_DELAY_CNT_MASK);
    eval 'sub DMA_CFG_CMB_ENB () {0x100000;}' unless defined(&DMA_CFG_CMB_ENB);
    eval 'sub DMA_CFG_SMB_ENB () {0x200000;}' unless defined(&DMA_CFG_SMB_ENB);
    eval 'sub DMA_CFG_CMB_NOW () {0x400000;}' unless defined(&DMA_CFG_CMB_NOW);
    eval 'sub DMA_CFG_SMB_DIS () {0x1000000;}' unless defined(&DMA_CFG_SMB_DIS);
    eval 'sub DMA_CFG_SMB_NOW () {0x80000000;}' unless defined(&DMA_CFG_SMB_NOW);
    eval 'sub DMA_CFG_RD_BURST_MASK () {0x7;}' unless defined(&DMA_CFG_RD_BURST_MASK);
    eval 'sub DMA_CFG_RD_BURST_SHIFT () {4;}' unless defined(&DMA_CFG_RD_BURST_SHIFT);
    eval 'sub DMA_CFG_WR_BURST_MASK () {0x7;}' unless defined(&DMA_CFG_WR_BURST_MASK);
    eval 'sub DMA_CFG_WR_BURST_SHIFT () {7;}' unless defined(&DMA_CFG_WR_BURST_SHIFT);
    eval 'sub DMA_CFG_RD_DELAY_CNT_SHIFT () {11;}' unless defined(&DMA_CFG_RD_DELAY_CNT_SHIFT);
    eval 'sub DMA_CFG_WR_DELAY_CNT_SHIFT () {16;}' unless defined(&DMA_CFG_WR_DELAY_CNT_SHIFT);
    eval 'sub DMA_CFG_RD_DELAY_CNT_DEFAULT () {15;}' unless defined(&DMA_CFG_RD_DELAY_CNT_DEFAULT);
    eval 'sub DMA_CFG_WR_DELAY_CNT_DEFAULT () {4;}' unless defined(&DMA_CFG_WR_DELAY_CNT_DEFAULT);
    eval 'sub ALC_SMB_STAT_TIMER () {0x15c4;}' unless defined(&ALC_SMB_STAT_TIMER);
    eval 'sub SMB_STAT_TIMER_MASK () {0xffffff;}' unless defined(&SMB_STAT_TIMER_MASK);
    eval 'sub SMB_STAT_TIMER_SHIFT () {0;}' unless defined(&SMB_STAT_TIMER_SHIFT);
    eval 'sub ALC_CMB_TD_THRESH () {0x15c8;}' unless defined(&ALC_CMB_TD_THRESH);
    eval 'sub CMB_TD_THRESH_MASK () {0xffff;}' unless defined(&CMB_TD_THRESH_MASK);
    eval 'sub CMB_TD_THRESH_SHIFT () {0;}' unless defined(&CMB_TD_THRESH_SHIFT);
    eval 'sub ALC_CMB_TX_TIMER () {0x15cc;}' unless defined(&ALC_CMB_TX_TIMER);
    eval 'sub CMB_TX_TIMER_MASK () {0xffff;}' unless defined(&CMB_TX_TIMER_MASK);
    eval 'sub CMB_TX_TIMER_SHIFT () {0;}' unless defined(&CMB_TX_TIMER_SHIFT);
    eval 'sub ALC_MBOX_RD0_PROD_IDX () {0x15e0;}' unless defined(&ALC_MBOX_RD0_PROD_IDX);
    eval 'sub ALC_MBOX_RD1_PROD_IDX () {0x15e4;}' unless defined(&ALC_MBOX_RD1_PROD_IDX);
    eval 'sub ALC_MBOX_RD2_PROD_IDX () {0x15e8;}' unless defined(&ALC_MBOX_RD2_PROD_IDX);
    eval 'sub ALC_MBOX_RD3_PROD_IDX () {0x15ec;}' unless defined(&ALC_MBOX_RD3_PROD_IDX);
    eval 'sub ALC_MBOX_RD_PROD_MASK () {0xffff;}' unless defined(&ALC_MBOX_RD_PROD_MASK);
    eval 'sub MBOX_RD_PROD_SHIFT () {0;}' unless defined(&MBOX_RD_PROD_SHIFT);
    eval 'sub ALC_MBOX_TD_PROD_IDX () {0x15f0;}' unless defined(&ALC_MBOX_TD_PROD_IDX);
    eval 'sub MBOX_TD_PROD_HI_IDX_MASK () {0xffff;}' unless defined(&MBOX_TD_PROD_HI_IDX_MASK);
    eval 'sub MBOX_TD_PROD_LO_IDX_MASK () {0xffff0000;}' unless defined(&MBOX_TD_PROD_LO_IDX_MASK);
    eval 'sub MBOX_TD_PROD_HI_IDX_SHIFT () {0;}' unless defined(&MBOX_TD_PROD_HI_IDX_SHIFT);
    eval 'sub MBOX_TD_PROD_LO_IDX_SHIFT () {16;}' unless defined(&MBOX_TD_PROD_LO_IDX_SHIFT);
    eval 'sub ALC_MBOX_TD_CONS_IDX () {0x15f4;}' unless defined(&ALC_MBOX_TD_CONS_IDX);
    eval 'sub MBOX_TD_CONS_HI_IDX_MASK () {0xffff;}' unless defined(&MBOX_TD_CONS_HI_IDX_MASK);
    eval 'sub MBOX_TD_CONS_LO_IDX_MASK () {0xffff0000;}' unless defined(&MBOX_TD_CONS_LO_IDX_MASK);
    eval 'sub MBOX_TD_CONS_HI_IDX_SHIFT () {0;}' unless defined(&MBOX_TD_CONS_HI_IDX_SHIFT);
    eval 'sub MBOX_TD_CONS_LO_IDX_SHIFT () {16;}' unless defined(&MBOX_TD_CONS_LO_IDX_SHIFT);
    eval 'sub ALC_MBOX_RD01_CONS_IDX () {0x15f8;}' unless defined(&ALC_MBOX_RD01_CONS_IDX);
    eval 'sub MBOX_RD0_CONS_IDX_MASK () {0xffff;}' unless defined(&MBOX_RD0_CONS_IDX_MASK);
    eval 'sub MBOX_RD1_CONS_IDX_MASK () {0xffff0000;}' unless defined(&MBOX_RD1_CONS_IDX_MASK);
    eval 'sub MBOX_RD0_CONS_IDX_SHIFT () {0;}' unless defined(&MBOX_RD0_CONS_IDX_SHIFT);
    eval 'sub MBOX_RD1_CONS_IDX_SHIFT () {16;}' unless defined(&MBOX_RD1_CONS_IDX_SHIFT);
    eval 'sub ALC_MBOX_RD23_CONS_IDX () {0x15fc;}' unless defined(&ALC_MBOX_RD23_CONS_IDX);
    eval 'sub MBOX_RD2_CONS_IDX_MASK () {0xffff;}' unless defined(&MBOX_RD2_CONS_IDX_MASK);
    eval 'sub MBOX_RD3_CONS_IDX_MASK () {0xffff0000;}' unless defined(&MBOX_RD3_CONS_IDX_MASK);
    eval 'sub MBOX_RD2_CONS_IDX_SHIFT () {0;}' unless defined(&MBOX_RD2_CONS_IDX_SHIFT);
    eval 'sub MBOX_RD3_CONS_IDX_SHIFT () {16;}' unless defined(&MBOX_RD3_CONS_IDX_SHIFT);
    eval 'sub ALC_INTR_STATUS () {0x1600;}' unless defined(&ALC_INTR_STATUS);
    eval 'sub INTR_SMB () {0x1;}' unless defined(&INTR_SMB);
    eval 'sub INTR_TIMER () {0x2;}' unless defined(&INTR_TIMER);
    eval 'sub INTR_MANUAL_TIMER () {0x4;}' unless defined(&INTR_MANUAL_TIMER);
    eval 'sub INTR_RX_FIFO_OFLOW () {0x8;}' unless defined(&INTR_RX_FIFO_OFLOW);
    eval 'sub INTR_RD0_UNDERRUN () {0x10;}' unless defined(&INTR_RD0_UNDERRUN);
    eval 'sub INTR_RD1_UNDERRUN () {0x20;}' unless defined(&INTR_RD1_UNDERRUN);
    eval 'sub INTR_RD2_UNDERRUN () {0x40;}' unless defined(&INTR_RD2_UNDERRUN);
    eval 'sub INTR_RD3_UNDERRUN () {0x80;}' unless defined(&INTR_RD3_UNDERRUN);
    eval 'sub INTR_TX_FIFO_UNDERRUN () {0x100;}' unless defined(&INTR_TX_FIFO_UNDERRUN);
    eval 'sub INTR_DMA_RD_TO_RST () {0x200;}' unless defined(&INTR_DMA_RD_TO_RST);
    eval 'sub INTR_DMA_WR_TO_RST () {0x400;}' unless defined(&INTR_DMA_WR_TO_RST);
    eval 'sub INTR_TX_CREDIT () {0x800;}' unless defined(&INTR_TX_CREDIT);
    eval 'sub INTR_GPHY () {0x1000;}' unless defined(&INTR_GPHY);
    eval 'sub INTR_GPHY_LOW_PW () {0x2000;}' unless defined(&INTR_GPHY_LOW_PW);
    eval 'sub INTR_TXQ_TO_RST () {0x4000;}' unless defined(&INTR_TXQ_TO_RST);
    eval 'sub INTR_TX_PKT () {0x8000;}' unless defined(&INTR_TX_PKT);
    eval 'sub INTR_RX_PKT0 () {0x10000;}' unless defined(&INTR_RX_PKT0);
    eval 'sub INTR_RX_PKT1 () {0x20000;}' unless defined(&INTR_RX_PKT1);
    eval 'sub INTR_RX_PKT2 () {0x40000;}' unless defined(&INTR_RX_PKT2);
    eval 'sub INTR_RX_PKT3 () {0x80000;}' unless defined(&INTR_RX_PKT3);
    eval 'sub INTR_MAC_RX () {0x100000;}' unless defined(&INTR_MAC_RX);
    eval 'sub INTR_MAC_TX () {0x200000;}' unless defined(&INTR_MAC_TX);
    eval 'sub INTR_UNDERRUN () {0x400000;}' unless defined(&INTR_UNDERRUN);
    eval 'sub INTR_FRAME_ERROR () {0x800000;}' unless defined(&INTR_FRAME_ERROR);
    eval 'sub INTR_FRAME_OK () {0x1000000;}' unless defined(&INTR_FRAME_OK);
    eval 'sub INTR_CSUM_ERROR () {0x2000000;}' unless defined(&INTR_CSUM_ERROR);
    eval 'sub INTR_PHY_LINK_DOWN () {0x4000000;}' unless defined(&INTR_PHY_LINK_DOWN);
    eval 'sub INTR_DIS_INT () {0x80000000;}' unless defined(&INTR_DIS_INT);
    eval 'sub ALC_INTR_MASK () {0x1604;}' unless defined(&ALC_INTR_MASK);
    if(defined(&notyet)) {
	eval 'sub INTR_RX_PKT () {( &INTR_RX_PKT0 |  &INTR_RX_PKT1 |  &INTR_RX_PKT2 |  &INTR_RX_PKT3);}' unless defined(&INTR_RX_PKT);
	eval 'sub INTR_RD_UNDERRUN () {( &INTR_RD0_UNDERRUN |  &INTR_RD1_UNDERRUN |  &INTR_RD2_UNDERRUN |  &INTR_RD3_UNDERRUN);}' unless defined(&INTR_RD_UNDERRUN);
    } else {
	eval 'sub INTR_RX_PKT () { &INTR_RX_PKT0;}' unless defined(&INTR_RX_PKT);
	eval 'sub INTR_RD_UNDERRUN () { &INTR_RD0_UNDERRUN;}' unless defined(&INTR_RD_UNDERRUN);
    }
    eval 'sub ALC_INTRS () {( &INTR_DMA_RD_TO_RST |  &INTR_DMA_WR_TO_RST |  &INTR_TXQ_TO_RST |  &INTR_RX_PKT |  &INTR_TX_PKT |  &INTR_RX_FIFO_OFLOW |  &INTR_RD_UNDERRUN |  &INTR_TX_FIFO_UNDERRUN);}' unless defined(&ALC_INTRS);
    eval 'sub ALC_INTR_RETRIG_TIMER () {0x1608;}' unless defined(&ALC_INTR_RETRIG_TIMER);
    eval 'sub INTR_RETRIG_TIMER_MASK () {0xffff;}' unless defined(&INTR_RETRIG_TIMER_MASK);
    eval 'sub INTR_RETRIG_TIMER_SHIFT () {0;}' unless defined(&INTR_RETRIG_TIMER_SHIFT);
    eval 'sub ALC_HDS_CFG () {0x160c;}' unless defined(&ALC_HDS_CFG);
    eval 'sub HDS_CFG_ENB () {0x1;}' unless defined(&HDS_CFG_ENB);
    eval 'sub HDS_CFG_BACKFILLSIZE_MASK () {0xfff00;}' unless defined(&HDS_CFG_BACKFILLSIZE_MASK);
    eval 'sub HDS_CFG_MAX_HDRSIZE_MASK () {0xfff00000;}' unless defined(&HDS_CFG_MAX_HDRSIZE_MASK);
    eval 'sub HDS_CFG_BACKFILLSIZE_SHIFT () {8;}' unless defined(&HDS_CFG_BACKFILLSIZE_SHIFT);
    eval 'sub HDS_CFG_MAX_HDRSIZE_SHIFT () {20;}' unless defined(&HDS_CFG_MAX_HDRSIZE_SHIFT);
    eval 'sub ALC_RX_MIB_BASE () {0x1700;}' unless defined(&ALC_RX_MIB_BASE);
    eval 'sub ALC_TX_MIB_BASE () {0x1760;}' unless defined(&ALC_TX_MIB_BASE);
    eval 'sub ALC_DEBUG_DATA0 () {0x1900;}' unless defined(&ALC_DEBUG_DATA0);
    eval 'sub ALC_DEBUG_DATA1 () {0x1904;}' unless defined(&ALC_DEBUG_DATA1);
    eval 'sub ALC_MII_DBG_ADDR () {0x1d;}' unless defined(&ALC_MII_DBG_ADDR);
    eval 'sub ALC_MII_DBG_DATA () {0x1e;}' unless defined(&ALC_MII_DBG_DATA);
    eval 'sub MII_ANA_CFG0 () {0x;}' unless defined(&MII_ANA_CFG0);
    eval 'sub ANA_RESTART_CAL () {0x1;}' unless defined(&ANA_RESTART_CAL);
    eval 'sub ANA_MANUL_SWICH_ON_MASK () {0x1e;}' unless defined(&ANA_MANUL_SWICH_ON_MASK);
    eval 'sub ANA_MAN_ENABLE () {0x20;}' unless defined(&ANA_MAN_ENABLE);
    eval 'sub ANA_SEL_HSP () {0x40;}' unless defined(&ANA_SEL_HSP);
    eval 'sub ANA_EN_HB () {0x80;}' unless defined(&ANA_EN_HB);
    eval 'sub ANA_EN_HBIAS () {0x100;}' unless defined(&ANA_EN_HBIAS);
    eval 'sub ANA_OEN_125M () {0x200;}' unless defined(&ANA_OEN_125M);
    eval 'sub ANA_EN_LCKDT () {0x400;}' unless defined(&ANA_EN_LCKDT);
    eval 'sub ANA_LCKDT_PHY () {0x800;}' unless defined(&ANA_LCKDT_PHY);
    eval 'sub ANA_AFE_MODE () {0x1000;}' unless defined(&ANA_AFE_MODE);
    eval 'sub ANA_VCO_SLOW () {0x2000;}' unless defined(&ANA_VCO_SLOW);
    eval 'sub ANA_VCO_FAST () {0x4000;}' unless defined(&ANA_VCO_FAST);
    eval 'sub ANA_SEL_CLK125M_DSP () {0x8000;}' unless defined(&ANA_SEL_CLK125M_DSP);
    eval 'sub ANA_MANUL_SWICH_ON_SHIFT () {1;}' unless defined(&ANA_MANUL_SWICH_ON_SHIFT);
    eval 'sub MII_ANA_CFG4 () {0x4;}' unless defined(&MII_ANA_CFG4);
    eval 'sub ANA_IECHO_ADJ_MASK () {0xf;}' unless defined(&ANA_IECHO_ADJ_MASK);
    eval 'sub ANA_IECHO_ADJ_3_MASK () {0xf;}' unless defined(&ANA_IECHO_ADJ_3_MASK);
    eval 'sub ANA_IECHO_ADJ_2_MASK () {0xf0;}' unless defined(&ANA_IECHO_ADJ_2_MASK);
    eval 'sub ANA_IECHO_ADJ_1_MASK () {0xf00;}' unless defined(&ANA_IECHO_ADJ_1_MASK);
    eval 'sub ANA_IECHO_ADJ_0_MASK () {0xf000;}' unless defined(&ANA_IECHO_ADJ_0_MASK);
    eval 'sub ANA_IECHO_ADJ_3_SHIFT () {0;}' unless defined(&ANA_IECHO_ADJ_3_SHIFT);
    eval 'sub ANA_IECHO_ADJ_2_SHIFT () {4;}' unless defined(&ANA_IECHO_ADJ_2_SHIFT);
    eval 'sub ANA_IECHO_ADJ_1_SHIFT () {8;}' unless defined(&ANA_IECHO_ADJ_1_SHIFT);
    eval 'sub ANA_IECHO_ADJ_0_SHIFT () {12;}' unless defined(&ANA_IECHO_ADJ_0_SHIFT);
    eval 'sub MII_ANA_CFG5 () {0x5;}' unless defined(&MII_ANA_CFG5);
    eval 'sub ANA_SERDES_CDR_BW_MASK () {0x3;}' unless defined(&ANA_SERDES_CDR_BW_MASK);
    eval 'sub ANA_MS_PAD_DBG () {0x4;}' unless defined(&ANA_MS_PAD_DBG);
    eval 'sub ANA_SPEEDUP_DBG () {0x8;}' unless defined(&ANA_SPEEDUP_DBG);
    eval 'sub ANA_SERDES_TH_LOS_MASK () {0x30;}' unless defined(&ANA_SERDES_TH_LOS_MASK);
    eval 'sub ANA_SERDES_EN_DEEM () {0x40;}' unless defined(&ANA_SERDES_EN_DEEM);
    eval 'sub ANA_SERDES_TXELECIDLE () {0x80;}' unless defined(&ANA_SERDES_TXELECIDLE);
    eval 'sub ANA_SERDES_BEACON () {0x100;}' unless defined(&ANA_SERDES_BEACON);
    eval 'sub ANA_SERDES_HALFTXDR () {0x200;}' unless defined(&ANA_SERDES_HALFTXDR);
    eval 'sub ANA_SERDES_SEL_HSP () {0x400;}' unless defined(&ANA_SERDES_SEL_HSP);
    eval 'sub ANA_SERDES_EN_PLL () {0x800;}' unless defined(&ANA_SERDES_EN_PLL);
    eval 'sub ANA_SERDES_EN () {0x1000;}' unless defined(&ANA_SERDES_EN);
    eval 'sub ANA_SERDES_EN_LCKDT () {0x2000;}' unless defined(&ANA_SERDES_EN_LCKDT);
    eval 'sub ANA_SERDES_CDR_BW_SHIFT () {0;}' unless defined(&ANA_SERDES_CDR_BW_SHIFT);
    eval 'sub ANA_SERDES_TH_LOS_SHIFT () {4;}' unless defined(&ANA_SERDES_TH_LOS_SHIFT);
    eval 'sub MII_ANA_CFG11 () {0xb;}' unless defined(&MII_ANA_CFG11);
    eval 'sub ANA_PS_HIB_EN () {0x8000;}' unless defined(&ANA_PS_HIB_EN);
    eval 'sub MII_ANA_CFG18 () {0x12;}' unless defined(&MII_ANA_CFG18);
    eval 'sub ANA_TEST_MODE_10BT_01MASK () {0x3;}' unless defined(&ANA_TEST_MODE_10BT_01MASK);
    eval 'sub ANA_LOOP_SEL_10BT () {0x4;}' unless defined(&ANA_LOOP_SEL_10BT);
    eval 'sub ANA_RGMII_MODE_SW () {0x8;}' unless defined(&ANA_RGMII_MODE_SW);
    eval 'sub ANA_EN_LONGECABLE () {0x10;}' unless defined(&ANA_EN_LONGECABLE);
    eval 'sub ANA_TEST_MODE_10BT_2 () {0x20;}' unless defined(&ANA_TEST_MODE_10BT_2);
    eval 'sub ANA_EN_10BT_IDLE () {0x400;}' unless defined(&ANA_EN_10BT_IDLE);
    eval 'sub ANA_EN_MASK_TB () {0x800;}' unless defined(&ANA_EN_MASK_TB);
    eval 'sub ANA_TRIGGER_SEL_TIMER_MASK () {0x3000;}' unless defined(&ANA_TRIGGER_SEL_TIMER_MASK);
    eval 'sub ANA_INTERVAL_SEL_TIMER_MASK () {0xc000;}' unless defined(&ANA_INTERVAL_SEL_TIMER_MASK);
    eval 'sub ANA_TEST_MODE_10BT_01SHIFT () {0;}' unless defined(&ANA_TEST_MODE_10BT_01SHIFT);
    eval 'sub ANA_TRIGGER_SEL_TIMER_SHIFT () {12;}' unless defined(&ANA_TRIGGER_SEL_TIMER_SHIFT);
    eval 'sub ANA_INTERVAL_SEL_TIMER_SHIFT () {14;}' unless defined(&ANA_INTERVAL_SEL_TIMER_SHIFT);
    eval 'sub MII_ANA_CFG41 () {0x29;}' unless defined(&MII_ANA_CFG41);
    eval 'sub ANA_TOP_PS_EN () {0x8000;}' unless defined(&ANA_TOP_PS_EN);
    eval 'sub MII_ANA_CFG54 () {0x36;}' unless defined(&MII_ANA_CFG54);
    eval 'sub ANA_LONG_CABLE_TH_100_MASK () {0x3f;}' unless defined(&ANA_LONG_CABLE_TH_100_MASK);
    eval 'sub ANA_DESERVED () {0x40;}' unless defined(&ANA_DESERVED);
    eval 'sub ANA_EN_LIT_CH () {0x80;}' unless defined(&ANA_EN_LIT_CH);
    eval 'sub ANA_SHORT_CABLE_TH_100_MASK () {0x3f00;}' unless defined(&ANA_SHORT_CABLE_TH_100_MASK);
    eval 'sub ANA_BP_BAD_LINK_ACCUM () {0x4000;}' unless defined(&ANA_BP_BAD_LINK_ACCUM);
    eval 'sub ANA_BP_SMALL_BW () {0x8000;}' unless defined(&ANA_BP_SMALL_BW);
    eval 'sub ANA_LONG_CABLE_TH_100_SHIFT () {0;}' unless defined(&ANA_LONG_CABLE_TH_100_SHIFT);
    eval 'sub ANA_SHORT_CABLE_TH_100_SHIFT () {8;}' unless defined(&ANA_SHORT_CABLE_TH_100_SHIFT);
    eval 'sub RRD_CSUM_MASK () {0xffff;}' unless defined(&RRD_CSUM_MASK);
    eval 'sub RRD_RD_CNT_MASK () {0xf0000;}' unless defined(&RRD_RD_CNT_MASK);
    eval 'sub RRD_RD_IDX_MASK () {0xfff00000;}' unless defined(&RRD_RD_IDX_MASK);
    eval 'sub RRD_CSUM_SHIFT () {0;}' unless defined(&RRD_CSUM_SHIFT);
    eval 'sub RRD_RD_CNT_SHIFT () {16;}' unless defined(&RRD_RD_CNT_SHIFT);
    eval 'sub RRD_RD_IDX_SHIFT () {20;}' unless defined(&RRD_RD_IDX_SHIFT);
    eval 'sub RRD_CSUM {
        my($x) = @_;
	    eval q(((($x) &  &RRD_CSUM_MASK) >>  &RRD_CSUM_SHIFT));
    }' unless defined(&RRD_CSUM);
    eval 'sub RRD_RD_CNT {
        my($x) = @_;
	    eval q(((($x) &  &RRD_RD_CNT_MASK) >>  &RRD_RD_CNT_SHIFT));
    }' unless defined(&RRD_RD_CNT);
    eval 'sub RRD_RD_IDX {
        my($x) = @_;
	    eval q(((($x) &  &RRD_RD_IDX_MASK) >>  &RRD_RD_IDX_SHIFT));
    }' unless defined(&RRD_RD_IDX);
    eval 'sub RRD_VLAN_MASK () {0xffff;}' unless defined(&RRD_VLAN_MASK);
    eval 'sub RRD_HEAD_LEN_MASK () {0xff0000;}' unless defined(&RRD_HEAD_LEN_MASK);
    eval 'sub RRD_HDS_MASK () {0x3000000;}' unless defined(&RRD_HDS_MASK);
    eval 'sub RRD_HDS_NONE () {0x;}' unless defined(&RRD_HDS_NONE);
    eval 'sub RRD_HDS_HEAD () {0x1000000;}' unless defined(&RRD_HDS_HEAD);
    eval 'sub RRD_HDS_DATA () {0x2000000;}' unless defined(&RRD_HDS_DATA);
    eval 'sub RRD_CPU_MASK () {0xc000000;}' unless defined(&RRD_CPU_MASK);
    eval 'sub RRD_HASH_FLAG_MASK () {0xf0000000;}' unless defined(&RRD_HASH_FLAG_MASK);
    eval 'sub RRD_VLAN_SHIFT () {0;}' unless defined(&RRD_VLAN_SHIFT);
    eval 'sub RRD_HEAD_LEN_SHIFT () {16;}' unless defined(&RRD_HEAD_LEN_SHIFT);
    eval 'sub RRD_HDS_SHIFT () {24;}' unless defined(&RRD_HDS_SHIFT);
    eval 'sub RRD_CPU_SHIFT () {26;}' unless defined(&RRD_CPU_SHIFT);
    eval 'sub RRD_HASH_FLAG_SHIFT () {28;}' unless defined(&RRD_HASH_FLAG_SHIFT);
    eval 'sub RRD_VLAN {
        my($x) = @_;
	    eval q(((($x) &  &RRD_VLAN_MASK) >>  &RRD_VLAN_SHIFT));
    }' unless defined(&RRD_VLAN);
    eval 'sub RRD_HEAD_LEN {
        my($x) = @_;
	    eval q(((($x) &  &RRD_HEAD_LEN_MASK) >>  &RRD_HEAD_LEN_SHIFT));
    }' unless defined(&RRD_HEAD_LEN);
    eval 'sub RRD_CPU {
        my($x) = @_;
	    eval q(((($x) &  &RRD_CPU_MASK) >>  &RRD_CPU_SHIFT));
    }' unless defined(&RRD_CPU);
    eval 'sub RRD_LEN_MASK () {0x3fff;}' unless defined(&RRD_LEN_MASK);
    eval 'sub RRD_LEN_SHIFT () {0;}' unless defined(&RRD_LEN_SHIFT);
    eval 'sub RRD_TCP_UDPCSUM_NOK () {0x4000;}' unless defined(&RRD_TCP_UDPCSUM_NOK);
    eval 'sub RRD_IPCSUM_NOK () {0x8000;}' unless defined(&RRD_IPCSUM_NOK);
    eval 'sub RRD_VLAN_TAG () {0x10000;}' unless defined(&RRD_VLAN_TAG);
    eval 'sub RRD_PROTO_MASK () {0xe0000;}' unless defined(&RRD_PROTO_MASK);
    eval 'sub RRD_PROTO_IPV4 () {0x20000;}' unless defined(&RRD_PROTO_IPV4);
    eval 'sub RRD_PROTO_IPV6 () {0xc0000;}' unless defined(&RRD_PROTO_IPV6);
    eval 'sub RRD_ERR_SUM () {0x100000;}' unless defined(&RRD_ERR_SUM);
    eval 'sub RRD_ERR_CRC () {0x200000;}' unless defined(&RRD_ERR_CRC);
    eval 'sub RRD_ERR_ALIGN () {0x400000;}' unless defined(&RRD_ERR_ALIGN);
    eval 'sub RRD_ERR_TRUNC () {0x800000;}' unless defined(&RRD_ERR_TRUNC);
    eval 'sub RRD_ERR_RUNT () {0x1000000;}' unless defined(&RRD_ERR_RUNT);
    eval 'sub RRD_ERR_ICMP () {0x2000000;}' unless defined(&RRD_ERR_ICMP);
    eval 'sub RRD_BCAST () {0x4000000;}' unless defined(&RRD_BCAST);
    eval 'sub RRD_MCAST () {0x8000000;}' unless defined(&RRD_MCAST);
    eval 'sub RRD_SNAP_LLC () {0x10000000;}' unless defined(&RRD_SNAP_LLC);
    eval 'sub RRD_ETHER () {0x;}' unless defined(&RRD_ETHER);
    eval 'sub RRD_FIFO_FULL () {0x20000000;}' unless defined(&RRD_FIFO_FULL);
    eval 'sub RRD_ERR_LENGTH () {0x40000000;}' unless defined(&RRD_ERR_LENGTH);
    eval 'sub RRD_VALID () {0x80000000;}' unless defined(&RRD_VALID);
    eval 'sub RRD_BYTES {
        my($x) = @_;
	    eval q(((($x) &  &RRD_LEN_MASK) >>  &RRD_LEN_SHIFT));
    }' unless defined(&RRD_BYTES);
    eval 'sub RRD_IPV4 {
        my($x) = @_;
	    eval q(((($x) &  &RRD_PROTO_MASK) ==  &RRD_PROTO_IPV4));
    }' unless defined(&RRD_IPV4);
    eval 'sub TD_BUFLEN_MASK () {0x3fff;}' unless defined(&TD_BUFLEN_MASK);
    eval 'sub TD_VLAN_MASK () {0xffff0000;}' unless defined(&TD_VLAN_MASK);
    eval 'sub TD_BUFLEN_SHIFT () {0;}' unless defined(&TD_BUFLEN_SHIFT);
    eval 'sub TX_BYTES {
        my($x) = @_;
	    eval q(((($x) <<  &TD_BUFLEN_SHIFT) &  &TD_BUFLEN_MASK));
    }' unless defined(&TX_BYTES);
    eval 'sub TD_VLAN_SHIFT () {16;}' unless defined(&TD_VLAN_SHIFT);
    eval 'sub TD_L4HDR_OFFSET_MASK () {0xff;}' unless defined(&TD_L4HDR_OFFSET_MASK);
    eval 'sub TD_TCPHDR_OFFSET_MASK () {0xff;}' unless defined(&TD_TCPHDR_OFFSET_MASK);
    eval 'sub TD_PLOAD_OFFSET_MASK () {0xff;}' unless defined(&TD_PLOAD_OFFSET_MASK);
    eval 'sub TD_CUSTOM_CSUM () {0x100;}' unless defined(&TD_CUSTOM_CSUM);
    eval 'sub TD_IPCSUM () {0x200;}' unless defined(&TD_IPCSUM);
    eval 'sub TD_TCPCSUM () {0x400;}' unless defined(&TD_TCPCSUM);
    eval 'sub TD_UDPCSUM () {0x800;}' unless defined(&TD_UDPCSUM);
    eval 'sub TD_TSO () {0x1000;}' unless defined(&TD_TSO);
    eval 'sub TD_TSO_DESCV1 () {0x;}' unless defined(&TD_TSO_DESCV1);
    eval 'sub TD_TSO_DESCV2 () {0x2000;}' unless defined(&TD_TSO_DESCV2);
    eval 'sub TD_CON_VLAN_TAG () {0x4000;}' unless defined(&TD_CON_VLAN_TAG);
    eval 'sub TD_INS_VLAN_TAG () {0x8000;}' unless defined(&TD_INS_VLAN_TAG);
    eval 'sub TD_IPV4_DESCV2 () {0x10000;}' unless defined(&TD_IPV4_DESCV2);
    eval 'sub TD_LLC_SNAP () {0x20000;}' unless defined(&TD_LLC_SNAP);
    eval 'sub TD_ETHERNET () {0x;}' unless defined(&TD_ETHERNET);
    eval 'sub TD_CUSTOM_CSUM_OFFSET_MASK () {0x3fc0000;}' unless defined(&TD_CUSTOM_CSUM_OFFSET_MASK);
    eval 'sub TD_CUSTOM_CSUM_EVEN_PAD () {0x40000000;}' unless defined(&TD_CUSTOM_CSUM_EVEN_PAD);
    eval 'sub TD_MSS_MASK () {0x7ffc0000;}' unless defined(&TD_MSS_MASK);
    eval 'sub TD_EOP () {0x80000000;}' unless defined(&TD_EOP);
    eval 'sub TD_L4HDR_OFFSET_SHIFT () {0;}' unless defined(&TD_L4HDR_OFFSET_SHIFT);
    eval 'sub TD_TCPHDR_OFFSET_SHIFT () {0;}' unless defined(&TD_TCPHDR_OFFSET_SHIFT);
    eval 'sub TD_PLOAD_OFFSET_SHIFT () {0;}' unless defined(&TD_PLOAD_OFFSET_SHIFT);
    eval 'sub TD_CUSTOM_CSUM_OFFSET_SHIFT () {18;}' unless defined(&TD_CUSTOM_CSUM_OFFSET_SHIFT);
    eval 'sub TD_MSS_SHIFT () {18;}' unless defined(&TD_MSS_SHIFT);
    eval 'sub ALC_TX_RING_CNT () {256;}' unless defined(&ALC_TX_RING_CNT);
    eval 'sub ALC_TX_RING_ALIGN () {$sizeof{\'struct tx_desc\'};}' unless defined(&ALC_TX_RING_ALIGN);
    eval 'sub ALC_RX_RING_CNT () {256;}' unless defined(&ALC_RX_RING_CNT);
    eval 'sub ALC_RX_RING_ALIGN () {$sizeof{\'struct rx_desc\'};}' unless defined(&ALC_RX_RING_ALIGN);
    eval 'sub ALC_RX_BUF_ALIGN () {4;}' unless defined(&ALC_RX_BUF_ALIGN);
    eval 'sub ALC_RR_RING_CNT () { &ALC_RX_RING_CNT;}' unless defined(&ALC_RR_RING_CNT);
    eval 'sub ALC_RR_RING_ALIGN () {$sizeof{\'struct rx_rdesc\'};}' unless defined(&ALC_RR_RING_ALIGN);
    eval 'sub ALC_CMB_ALIGN () {8;}' unless defined(&ALC_CMB_ALIGN);
    eval 'sub ALC_SMB_ALIGN () {8;}' unless defined(&ALC_SMB_ALIGN);
    eval 'sub ALC_TSO_MAXSEGSIZE () {4096;}' unless defined(&ALC_TSO_MAXSEGSIZE);
    eval 'sub ALC_TSO_MAXSIZE () {(65535+ $sizeof{\'struct ether_vlan_header\'});}' unless defined(&ALC_TSO_MAXSIZE);
    eval 'sub ALC_MAXTXSEGS () {32;}' unless defined(&ALC_MAXTXSEGS);
    eval 'sub ALC_ADDR_LO {
        my($x) = @_;
	    eval q((( &uint64_t) ($x) & 0xffffffff));
    }' unless defined(&ALC_ADDR_LO);
    eval 'sub ALC_ADDR_HI {
        my($x) = @_;
	    eval q((( &uint64_t) ($x) >> 32));
    }' unless defined(&ALC_ADDR_HI);
    eval 'sub ALC_DESC_INC {
        my($x, $y) = @_;
	    eval q((($x) = (($x) + 1) % ($y)));
    }' unless defined(&ALC_DESC_INC);
    eval 'sub ALC_TX_DESC_HIWAT () {(( &ALC_TX_RING_CNT * 6) / 10);}' unless defined(&ALC_TX_DESC_HIWAT);
    eval 'sub ALC_MSI_MESSAGES () {1;}' unless defined(&ALC_MSI_MESSAGES);
    eval 'sub ALC_MSIX_MESSAGES () {1;}' unless defined(&ALC_MSIX_MESSAGES);
    eval 'sub ALC_TX_RING_SZ () {($sizeof{\'struct tx_desc\'} *  &ALC_TX_RING_CNT);}' unless defined(&ALC_TX_RING_SZ);
    eval 'sub ALC_RX_RING_SZ () {($sizeof{\'struct rx_desc\'} *  &ALC_RX_RING_CNT);}' unless defined(&ALC_RX_RING_SZ);
    eval 'sub ALC_RR_RING_SZ () {($sizeof{\'struct rx_rdesc\'} *  &ALC_RR_RING_CNT);}' unless defined(&ALC_RR_RING_SZ);
    eval 'sub ALC_CMB_SZ () {($sizeof{\'struct cmb\'});}' unless defined(&ALC_CMB_SZ);
    eval 'sub ALC_SMB_SZ () {($sizeof{\'struct smb\'});}' unless defined(&ALC_SMB_SZ);
    eval 'sub ALC_PROC_MIN () {16;}' unless defined(&ALC_PROC_MIN);
    eval 'sub ALC_PROC_MAX () {( &ALC_RX_RING_CNT - 1);}' unless defined(&ALC_PROC_MAX);
    eval 'sub ALC_PROC_DEFAULT () {( &ALC_RX_RING_CNT / 4);}' unless defined(&ALC_PROC_DEFAULT);
    eval 'sub ALC_JUMBO_FRAMELEN () {(9* 1024);}' unless defined(&ALC_JUMBO_FRAMELEN);
    eval 'sub ALC_JUMBO_MTU () {( &ALC_JUMBO_FRAMELEN - $sizeof{\'struct ether_vlan_header\'} -  &ETHER_CRC_LEN);}' unless defined(&ALC_JUMBO_MTU);
    eval 'sub ALC_MAX_FRAMELEN () {( &ETHER_MAX_LEN +  &EVL_ENCAPLEN);}' unless defined(&ALC_MAX_FRAMELEN);
    eval 'sub ALC_TSO_MTU () {(6* 1024);}' unless defined(&ALC_TSO_MTU);
    eval 'sub ALC_FLAG_PCIE () {0x1;}' unless defined(&ALC_FLAG_PCIE);
    eval 'sub ALC_FLAG_PCIX () {0x2;}' unless defined(&ALC_FLAG_PCIX);
    eval 'sub ALC_FLAG_MSI () {0x4;}' unless defined(&ALC_FLAG_MSI);
    eval 'sub ALC_FLAG_MSIX () {0x8;}' unless defined(&ALC_FLAG_MSIX);
    eval 'sub ALC_FLAG_FASTETHER () {0x20;}' unless defined(&ALC_FLAG_FASTETHER);
    eval 'sub ALC_FLAG_JUMBO () {0x40;}' unless defined(&ALC_FLAG_JUMBO);
    eval 'sub ALC_FLAG_ASPM_MON () {0x80;}' unless defined(&ALC_FLAG_ASPM_MON);
    eval 'sub ALC_FLAG_CMB_BUG () {0x100;}' unless defined(&ALC_FLAG_CMB_BUG);
    eval 'sub ALC_FLAG_SMB_BUG () {0x200;}' unless defined(&ALC_FLAG_SMB_BUG);
    eval 'sub ALC_FLAG_DETACH () {0x4000;}' unless defined(&ALC_FLAG_DETACH);
    eval 'sub ALC_FLAG_LINK () {0x8000;}' unless defined(&ALC_FLAG_LINK);
    eval 'sub CSR_WRITE_4 {
        my($_sc, $reg, $val) = @_;
	    eval q( &bus_space_write_4(( &sc)-> &sc_mem_bt, ( &sc)-> &sc_mem_bh, ($reg), ($val)));
    }' unless defined(&CSR_WRITE_4);
    eval 'sub CSR_WRITE_2 {
        my($_sc, $reg, $val) = @_;
	    eval q( &bus_space_write_2(( &sc)-> &sc_mem_bt, ( &sc)-> &sc_mem_bh, ($reg), ($val)));
    }' unless defined(&CSR_WRITE_2);
    eval 'sub CSR_WRITE_1 {
        my($_sc, $reg, $val) = @_;
	    eval q( &bus_space_write_1(( &sc)-> &sc_mem_bt, ( &sc)-> &sc_mem_bh, ($reg), ($val)));
    }' unless defined(&CSR_WRITE_1);
    eval 'sub CSR_READ_2 {
        my($_sc, $reg) = @_;
	    eval q( &bus_space_read_2(( &sc)-> &sc_mem_bt, ( &sc)-> &sc_mem_bh, ($reg)));
    }' unless defined(&CSR_READ_2);
    eval 'sub CSR_READ_4 {
        my($_sc, $reg) = @_;
	    eval q( &bus_space_read_4(( &sc)-> &sc_mem_bt, ( &sc)-> &sc_mem_bh, ($reg)));
    }' unless defined(&CSR_READ_4);
    eval 'sub ALC_RXCHAIN_RESET {
        my($_sc) = @_;
	    eval q( &do { ($_sc)-> ($alc_cdata->{alc_rxhead}) =  &NULL; ($_sc)-> ($alc_cdata->{alc_rxtail}) =  &NULL; ($_sc)-> ($alc_cdata->{alc_rxprev_tail}) =  &NULL; ($_sc)-> ($alc_cdata->{alc_rxlen}) = 0; }  &while (0));
    }' unless defined(&ALC_RXCHAIN_RESET);
    eval 'sub ALC_TX_TIMEOUT () {5;}' unless defined(&ALC_TX_TIMEOUT);
    eval 'sub ALC_RESET_TIMEOUT () {100;}' unless defined(&ALC_RESET_TIMEOUT);
    eval 'sub ALC_TIMEOUT () {1000;}' unless defined(&ALC_TIMEOUT);
    eval 'sub ALC_PHY_TIMEOUT () {1000;}' unless defined(&ALC_PHY_TIMEOUT);
}
1;
