require '_h2ph_pre.ph';

no warnings qw(redefine misc);

unless(defined(&_IF_AGEREG_H)) {
    eval 'sub _IF_AGEREG_H () {1;}' unless defined(&_IF_AGEREG_H);
    eval 'sub AGE_PCIR_BAR () {0x10;}' unless defined(&AGE_PCIR_BAR);
    eval 'sub VENDORID_ATTANSIC () {0x1969;}' unless defined(&VENDORID_ATTANSIC);
    eval 'sub DEVICEID_ATTANSIC_L1 () {0x1048;}' unless defined(&DEVICEID_ATTANSIC_L1);
    eval 'sub AGE_VPD_REG_CONF_START () {0x100;}' unless defined(&AGE_VPD_REG_CONF_START);
    eval 'sub AGE_VPD_REG_CONF_END () {0x1ff;}' unless defined(&AGE_VPD_REG_CONF_END);
    eval 'sub AGE_VPD_REG_CONF_SIG () {0x5a;}' unless defined(&AGE_VPD_REG_CONF_SIG);
    eval 'sub AGE_SPI_CTRL () {0x200;}' unless defined(&AGE_SPI_CTRL);
    eval 'sub SPI_STAT_NOT_READY () {0x1;}' unless defined(&SPI_STAT_NOT_READY);
    eval 'sub SPI_STAT_WR_ENB () {0x2;}' unless defined(&SPI_STAT_WR_ENB);
    eval 'sub SPI_STAT_WRP_ENB () {0x80;}' unless defined(&SPI_STAT_WRP_ENB);
    eval 'sub SPI_INST_MASK () {0xff;}' unless defined(&SPI_INST_MASK);
    eval 'sub SPI_START () {0x100;}' unless defined(&SPI_START);
    eval 'sub SPI_INST_START () {0x800;}' unless defined(&SPI_INST_START);
    eval 'sub SPI_VPD_ENB () {0x2000;}' unless defined(&SPI_VPD_ENB);
    eval 'sub SPI_LOADER_START () {0x8000;}' unless defined(&SPI_LOADER_START);
    eval 'sub SPI_CS_HI_MASK () {0x30000;}' unless defined(&SPI_CS_HI_MASK);
    eval 'sub SPI_CS_HOLD_MASK () {0xc0000;}' unless defined(&SPI_CS_HOLD_MASK);
    eval 'sub SPI_CLK_LO_MASK () {0x300000;}' unless defined(&SPI_CLK_LO_MASK);
    eval 'sub SPI_CLK_HI_MASK () {0xc00000;}' unless defined(&SPI_CLK_HI_MASK);
    eval 'sub SPI_CS_SETUP_MASK () {0x3000000;}' unless defined(&SPI_CS_SETUP_MASK);
    eval 'sub SPI_EPROM_PG_MASK () {0xc000000;}' unless defined(&SPI_EPROM_PG_MASK);
    eval 'sub SPI_INST_SHIFT () {8;}' unless defined(&SPI_INST_SHIFT);
    eval 'sub SPI_CS_HI_SHIFT () {16;}' unless defined(&SPI_CS_HI_SHIFT);
    eval 'sub SPI_CS_HOLD_SHIFT () {18;}' unless defined(&SPI_CS_HOLD_SHIFT);
    eval 'sub SPI_CLK_LO_SHIFT () {20;}' unless defined(&SPI_CLK_LO_SHIFT);
    eval 'sub SPI_CLK_HI_SHIFT () {22;}' unless defined(&SPI_CLK_HI_SHIFT);
    eval 'sub SPI_CS_SETUP_SHIFT () {24;}' unless defined(&SPI_CS_SETUP_SHIFT);
    eval 'sub SPI_EPROM_PG_SHIFT () {26;}' unless defined(&SPI_EPROM_PG_SHIFT);
    eval 'sub SPI_WAIT_READY () {0x10000000;}' unless defined(&SPI_WAIT_READY);
    eval 'sub AGE_SPI_ADDR () {0x204;}' unless defined(&AGE_SPI_ADDR);
    eval 'sub AGE_SPI_DATA () {0x208;}' unless defined(&AGE_SPI_DATA);
    eval 'sub AGE_SPI_CONFIG () {0x20c;}' unless defined(&AGE_SPI_CONFIG);
    eval 'sub AGE_SPI_OP_PROGRAM () {0x210;}' unless defined(&AGE_SPI_OP_PROGRAM);
    eval 'sub AGE_SPI_OP_SC_ERASE () {0x211;}' unless defined(&AGE_SPI_OP_SC_ERASE);
    eval 'sub AGE_SPI_OP_CHIP_ERASE () {0x212;}' unless defined(&AGE_SPI_OP_CHIP_ERASE);
    eval 'sub AGE_SPI_OP_RDID () {0x213;}' unless defined(&AGE_SPI_OP_RDID);
    eval 'sub AGE_SPI_OP_WREN () {0x214;}' unless defined(&AGE_SPI_OP_WREN);
    eval 'sub AGE_SPI_OP_RDSR () {0x215;}' unless defined(&AGE_SPI_OP_RDSR);
    eval 'sub AGE_SPI_OP_WRSR () {0x216;}' unless defined(&AGE_SPI_OP_WRSR);
    eval 'sub AGE_SPI_OP_READ () {0x217;}' unless defined(&AGE_SPI_OP_READ);
    eval 'sub AGE_TWSI_CTRL () {0x218;}' unless defined(&AGE_TWSI_CTRL);
    eval 'sub TWSI_CTRL_SW_LD_START () {0x800;}' unless defined(&TWSI_CTRL_SW_LD_START);
    eval 'sub TWSI_CTRL_HW_LD_START () {0x1000;}' unless defined(&TWSI_CTRL_HW_LD_START);
    eval 'sub TWSI_CTRL_LD_EXIST () {0x400000;}' unless defined(&TWSI_CTRL_LD_EXIST);
    eval 'sub AGE_DEV_MISC_CTRL () {0x21c;}' unless defined(&AGE_DEV_MISC_CTRL);
    eval 'sub AGE_MASTER_CFG () {0x1400;}' unless defined(&AGE_MASTER_CFG);
    eval 'sub MASTER_RESET () {0x1;}' unless defined(&MASTER_RESET);
    eval 'sub MASTER_MTIMER_ENB () {0x2;}' unless defined(&MASTER_MTIMER_ENB);
    eval 'sub MASTER_ITIMER_ENB () {0x4;}' unless defined(&MASTER_ITIMER_ENB);
    eval 'sub MASTER_MANUAL_INT_ENB () {0x8;}' unless defined(&MASTER_MANUAL_INT_ENB);
    eval 'sub MASTER_CHIP_REV_MASK () {0xff0000;}' unless defined(&MASTER_CHIP_REV_MASK);
    eval 'sub MASTER_CHIP_ID_MASK () {0xff000000;}' unless defined(&MASTER_CHIP_ID_MASK);
    eval 'sub MASTER_CHIP_REV_SHIFT () {16;}' unless defined(&MASTER_CHIP_REV_SHIFT);
    eval 'sub MASTER_CHIP_ID_SHIFT () {24;}' unless defined(&MASTER_CHIP_ID_SHIFT);
    eval 'sub AGE_TICK_USECS () {2;}' unless defined(&AGE_TICK_USECS);
    eval 'sub AGE_USECS {
        my($x) = @_;
	    eval q((($x) /  &AGE_TICK_USECS));
    }' unless defined(&AGE_USECS);
    eval 'sub AGE_MANUAL_TIMER () {0x1404;}' unless defined(&AGE_MANUAL_TIMER);
    eval 'sub AGE_IM_TIMER () {0x1408;}' unless defined(&AGE_IM_TIMER);
    eval 'sub AGE_IM_TIMER_MIN () {0;}' unless defined(&AGE_IM_TIMER_MIN);
    eval 'sub AGE_IM_TIMER_MAX () {130000;}' unless defined(&AGE_IM_TIMER_MAX);
    eval 'sub AGE_IM_TIMER_DEFAULT () {100;}' unless defined(&AGE_IM_TIMER_DEFAULT);
    eval 'sub AGE_GPHY_CTRL () {0x140c;}' unless defined(&AGE_GPHY_CTRL);
    eval 'sub GPHY_CTRL_RST () {0x;}' unless defined(&GPHY_CTRL_RST);
    eval 'sub GPHY_CTRL_CLR () {0x1;}' unless defined(&GPHY_CTRL_CLR);
    eval 'sub AGE_INTR_CLR_TIMER () {0x140e;}' unless defined(&AGE_INTR_CLR_TIMER);
    eval 'sub AGE_IDLE_STATUS () {0x1410;}' unless defined(&AGE_IDLE_STATUS);
    eval 'sub IDLE_STATUS_RXMAC () {0x1;}' unless defined(&IDLE_STATUS_RXMAC);
    eval 'sub IDLE_STATUS_TXMAC () {0x2;}' unless defined(&IDLE_STATUS_TXMAC);
    eval 'sub IDLE_STATUS_RXQ () {0x4;}' unless defined(&IDLE_STATUS_RXQ);
    eval 'sub IDLE_STATUS_TXQ () {0x8;}' unless defined(&IDLE_STATUS_TXQ);
    eval 'sub IDLE_STATUS_DMARD () {0x10;}' unless defined(&IDLE_STATUS_DMARD);
    eval 'sub IDLE_STATUS_DMAWR () {0x20;}' unless defined(&IDLE_STATUS_DMAWR);
    eval 'sub IDLE_STATUS_SMB () {0x40;}' unless defined(&IDLE_STATUS_SMB);
    eval 'sub IDLE_STATUS_CMB () {0x80;}' unless defined(&IDLE_STATUS_CMB);
    eval 'sub AGE_MDIO () {0x1414;}' unless defined(&AGE_MDIO);
    eval 'sub MDIO_DATA_MASK () {0xffff;}' unless defined(&MDIO_DATA_MASK);
    eval 'sub MDIO_REG_ADDR_MASK () {0x1f0000;}' unless defined(&MDIO_REG_ADDR_MASK);
    eval 'sub MDIO_OP_READ () {0x200000;}' unless defined(&MDIO_OP_READ);
    eval 'sub MDIO_OP_WRITE () {0x;}' unless defined(&MDIO_OP_WRITE);
    eval 'sub MDIO_SUP_PREAMBLE () {0x400000;}' unless defined(&MDIO_SUP_PREAMBLE);
    eval 'sub MDIO_OP_EXECUTE () {0x800000;}' unless defined(&MDIO_OP_EXECUTE);
    eval 'sub MDIO_CLK_25_4 () {0x;}' unless defined(&MDIO_CLK_25_4);
    eval 'sub MDIO_CLK_25_6 () {0x2000000;}' unless defined(&MDIO_CLK_25_6);
    eval 'sub MDIO_CLK_25_8 () {0x3000000;}' unless defined(&MDIO_CLK_25_8);
    eval 'sub MDIO_CLK_25_10 () {0x4000000;}' unless defined(&MDIO_CLK_25_10);
    eval 'sub MDIO_CLK_25_14 () {0x5000000;}' unless defined(&MDIO_CLK_25_14);
    eval 'sub MDIO_CLK_25_20 () {0x6000000;}' unless defined(&MDIO_CLK_25_20);
    eval 'sub MDIO_CLK_25_28 () {0x7000000;}' unless defined(&MDIO_CLK_25_28);
    eval 'sub MDIO_OP_BUSY () {0x8000000;}' unless defined(&MDIO_OP_BUSY);
    eval 'sub MDIO_DATA_SHIFT () {0;}' unless defined(&MDIO_DATA_SHIFT);
    eval 'sub MDIO_REG_ADDR_SHIFT () {16;}' unless defined(&MDIO_REG_ADDR_SHIFT);
    eval 'sub MDIO_REG_ADDR {
        my($x) = @_;
	    eval q(((($x) <<  &MDIO_REG_ADDR_SHIFT) &  &MDIO_REG_ADDR_MASK));
    }' unless defined(&MDIO_REG_ADDR);
    eval 'sub AGE_PHY_ADDR () {0;}' unless defined(&AGE_PHY_ADDR);
    eval 'sub AGE_PHY_STATUS () {0x1418;}' unless defined(&AGE_PHY_STATUS);
    eval 'sub AGE_BIST0 () {0x141c;}' unless defined(&AGE_BIST0);
    eval 'sub BIST0_ENB () {0x1;}' unless defined(&BIST0_ENB);
    eval 'sub BIST0_SRAM_FAIL () {0x2;}' unless defined(&BIST0_SRAM_FAIL);
    eval 'sub BIST0_FUSE_FLAG () {0x4;}' unless defined(&BIST0_FUSE_FLAG);
    eval 'sub AGE_BIST1 () {0x1420;}' unless defined(&AGE_BIST1);
    eval 'sub BIST1_ENB () {0x1;}' unless defined(&BIST1_ENB);
    eval 'sub BIST1_SRAM_FAIL () {0x2;}' unless defined(&BIST1_SRAM_FAIL);
    eval 'sub BIST1_FUSE_FLAG () {0x4;}' unless defined(&BIST1_FUSE_FLAG);
    eval 'sub AGE_MAC_CFG () {0x1480;}' unless defined(&AGE_MAC_CFG);
    eval 'sub MAC_CFG_TX_ENB () {0x1;}' unless defined(&MAC_CFG_TX_ENB);
    eval 'sub MAC_CFG_RX_ENB () {0x2;}' unless defined(&MAC_CFG_RX_ENB);
    eval 'sub MAC_CFG_TX_FC () {0x4;}' unless defined(&MAC_CFG_TX_FC);
    eval 'sub MAC_CFG_RX_FC () {0x8;}' unless defined(&MAC_CFG_RX_FC);
    eval 'sub MAC_CFG_LOOP () {0x10;}' unless defined(&MAC_CFG_LOOP);
    eval 'sub MAC_CFG_FULL_DUPLEX () {0x20;}' unless defined(&MAC_CFG_FULL_DUPLEX);
    eval 'sub MAC_CFG_TX_CRC_ENB () {0x40;}' unless defined(&MAC_CFG_TX_CRC_ENB);
    eval 'sub MAC_CFG_TX_AUTO_PAD () {0x80;}' unless defined(&MAC_CFG_TX_AUTO_PAD);
    eval 'sub MAC_CFG_TX_LENCHK () {0x100;}' unless defined(&MAC_CFG_TX_LENCHK);
    eval 'sub MAC_CFG_RX_JUMBO_ENB () {0x200;}' unless defined(&MAC_CFG_RX_JUMBO_ENB);
    eval 'sub MAC_CFG_PREAMBLE_MASK () {0x3c00;}' unless defined(&MAC_CFG_PREAMBLE_MASK);
    eval 'sub MAC_CFG_VLAN_TAG_STRIP () {0x4000;}' unless defined(&MAC_CFG_VLAN_TAG_STRIP);
    eval 'sub MAC_CFG_PROMISC () {0x8000;}' unless defined(&MAC_CFG_PROMISC);
    eval 'sub MAC_CFG_TX_PAUSE () {0x10000;}' unless defined(&MAC_CFG_TX_PAUSE);
    eval 'sub MAC_CFG_SCNT () {0x20000;}' unless defined(&MAC_CFG_SCNT);
    eval 'sub MAC_CFG_SYNC_RST_TX () {0x40000;}' unless defined(&MAC_CFG_SYNC_RST_TX);
    eval 'sub MAC_CFG_SPEED_MASK () {0x300000;}' unless defined(&MAC_CFG_SPEED_MASK);
    eval 'sub MAC_CFG_SPEED_10_100 () {0x100000;}' unless defined(&MAC_CFG_SPEED_10_100);
    eval 'sub MAC_CFG_SPEED_1000 () {0x200000;}' unless defined(&MAC_CFG_SPEED_1000);
    eval 'sub MAC_CFG_DBG_TX_BACKOFF () {0x400000;}' unless defined(&MAC_CFG_DBG_TX_BACKOFF);
    eval 'sub MAC_CFG_TX_JUMBO_ENB () {0x800000;}' unless defined(&MAC_CFG_TX_JUMBO_ENB);
    eval 'sub MAC_CFG_RXCSUM_ENB () {0x1000000;}' unless defined(&MAC_CFG_RXCSUM_ENB);
    eval 'sub MAC_CFG_ALLMULTI () {0x2000000;}' unless defined(&MAC_CFG_ALLMULTI);
    eval 'sub MAC_CFG_BCAST () {0x4000000;}' unless defined(&MAC_CFG_BCAST);
    eval 'sub MAC_CFG_DBG () {0x8000000;}' unless defined(&MAC_CFG_DBG);
    eval 'sub MAC_CFG_PREAMBLE_SHIFT () {10;}' unless defined(&MAC_CFG_PREAMBLE_SHIFT);
    eval 'sub MAC_CFG_PREAMBLE_DEFAULT () {7;}' unless defined(&MAC_CFG_PREAMBLE_DEFAULT);
    eval 'sub AGE_IPG_IFG_CFG () {0x1484;}' unless defined(&AGE_IPG_IFG_CFG);
    eval 'sub IPG_IFG_IPGT_MASK () {0x7f;}' unless defined(&IPG_IFG_IPGT_MASK);
    eval 'sub IPG_IFG_MIFG_MASK () {0xff00;}' unless defined(&IPG_IFG_MIFG_MASK);
    eval 'sub IPG_IFG_IPG1_MASK () {0x7f0000;}' unless defined(&IPG_IFG_IPG1_MASK);
    eval 'sub IPG_IFG_IPG2_MASK () {0x7f000000;}' unless defined(&IPG_IFG_IPG2_MASK);
    eval 'sub IPG_IFG_IPGT_SHIFT () {0;}' unless defined(&IPG_IFG_IPGT_SHIFT);
    eval 'sub IPG_IFG_IPGT_DEFAULT () {0x60;}' unless defined(&IPG_IFG_IPGT_DEFAULT);
    eval 'sub IPG_IFG_MIFG_SHIFT () {8;}' unless defined(&IPG_IFG_MIFG_SHIFT);
    eval 'sub IPG_IFG_MIFG_DEFAULT () {0x50;}' unless defined(&IPG_IFG_MIFG_DEFAULT);
    eval 'sub IPG_IFG_IPG1_SHIFT () {16;}' unless defined(&IPG_IFG_IPG1_SHIFT);
    eval 'sub IPG_IFG_IPG1_DEFAULT () {0x40;}' unless defined(&IPG_IFG_IPG1_DEFAULT);
    eval 'sub IPG_IFG_IPG2_SHIFT () {24;}' unless defined(&IPG_IFG_IPG2_SHIFT);
    eval 'sub IPG_IFG_IPG2_DEFAULT () {0x60;}' unless defined(&IPG_IFG_IPG2_DEFAULT);
    eval 'sub AGE_PAR0 () {0x1488;}' unless defined(&AGE_PAR0);
    eval 'sub AGE_PAR1 () {0x148c;}' unless defined(&AGE_PAR1);
    eval 'sub AGE_MAR0 () {0x1490;}' unless defined(&AGE_MAR0);
    eval 'sub AGE_MAR1 () {0x1494;}' unless defined(&AGE_MAR1);
    eval 'sub AGE_HDPX_CFG () {0x1498;}' unless defined(&AGE_HDPX_CFG);
    eval 'sub HDPX_CFG_LCOL_MASK () {0x3ff;}' unless defined(&HDPX_CFG_LCOL_MASK);
    eval 'sub HDPX_CFG_RETRY_MASK () {0xf000;}' unless defined(&HDPX_CFG_RETRY_MASK);
    eval 'sub HDPX_CFG_EXC_DEF_EN () {0x10000;}' unless defined(&HDPX_CFG_EXC_DEF_EN);
    eval 'sub HDPX_CFG_NO_BACK_C () {0x20000;}' unless defined(&HDPX_CFG_NO_BACK_C);
    eval 'sub HDPX_CFG_NO_BACK_P () {0x40000;}' unless defined(&HDPX_CFG_NO_BACK_P);
    eval 'sub HDPX_CFG_ABEBE () {0x80000;}' unless defined(&HDPX_CFG_ABEBE);
    eval 'sub HDPX_CFG_ABEBT_MASK () {0xf00000;}' unless defined(&HDPX_CFG_ABEBT_MASK);
    eval 'sub HDPX_CFG_JAMIPG_MASK () {0xf000000;}' unless defined(&HDPX_CFG_JAMIPG_MASK);
    eval 'sub HDPX_CFG_LCOL_SHIFT () {0;}' unless defined(&HDPX_CFG_LCOL_SHIFT);
    eval 'sub HDPX_CFG_LCOL_DEFAULT () {0x37;}' unless defined(&HDPX_CFG_LCOL_DEFAULT);
    eval 'sub HDPX_CFG_RETRY_SHIFT () {12;}' unless defined(&HDPX_CFG_RETRY_SHIFT);
    eval 'sub HDPX_CFG_RETRY_DEFAULT () {0xf;}' unless defined(&HDPX_CFG_RETRY_DEFAULT);
    eval 'sub HDPX_CFG_ABEBT_SHIFT () {20;}' unless defined(&HDPX_CFG_ABEBT_SHIFT);
    eval 'sub HDPX_CFG_ABEBT_DEFAULT () {0xa;}' unless defined(&HDPX_CFG_ABEBT_DEFAULT);
    eval 'sub HDPX_CFG_JAMIPG_SHIFT () {24;}' unless defined(&HDPX_CFG_JAMIPG_SHIFT);
    eval 'sub HDPX_CFG_JAMIPG_DEFAULT () {0x7;}' unless defined(&HDPX_CFG_JAMIPG_DEFAULT);
    eval 'sub AGE_FRAME_SIZE () {0x149c;}' unless defined(&AGE_FRAME_SIZE);
    eval 'sub AGE_WOL_CFG () {0x14a0;}' unless defined(&AGE_WOL_CFG);
    eval 'sub WOL_CFG_PATTERN () {0x1;}' unless defined(&WOL_CFG_PATTERN);
    eval 'sub WOL_CFG_PATTERN_ENB () {0x2;}' unless defined(&WOL_CFG_PATTERN_ENB);
    eval 'sub WOL_CFG_MAGIC () {0x4;}' unless defined(&WOL_CFG_MAGIC);
    eval 'sub WOL_CFG_MAGIC_ENB () {0x8;}' unless defined(&WOL_CFG_MAGIC_ENB);
    eval 'sub WOL_CFG_LINK_CHG () {0x10;}' unless defined(&WOL_CFG_LINK_CHG);
    eval 'sub WOL_CFG_LINK_CHG_ENB () {0x20;}' unless defined(&WOL_CFG_LINK_CHG_ENB);
    eval 'sub WOL_CFG_PATTERN_DET () {0x100;}' unless defined(&WOL_CFG_PATTERN_DET);
    eval 'sub WOL_CFG_MAGIC_DET () {0x200;}' unless defined(&WOL_CFG_MAGIC_DET);
    eval 'sub WOL_CFG_LINK_CHG_DET () {0x400;}' unless defined(&WOL_CFG_LINK_CHG_DET);
    eval 'sub WOL_CFG_CLK_SWITCH_ENB () {0x8000;}' unless defined(&WOL_CFG_CLK_SWITCH_ENB);
    eval 'sub WOL_CFG_PATTERN0 () {0x10000;}' unless defined(&WOL_CFG_PATTERN0);
    eval 'sub WOL_CFG_PATTERN1 () {0x20000;}' unless defined(&WOL_CFG_PATTERN1);
    eval 'sub WOL_CFG_PATTERN2 () {0x40000;}' unless defined(&WOL_CFG_PATTERN2);
    eval 'sub WOL_CFG_PATTERN3 () {0x80000;}' unless defined(&WOL_CFG_PATTERN3);
    eval 'sub WOL_CFG_PATTERN4 () {0x100000;}' unless defined(&WOL_CFG_PATTERN4);
    eval 'sub WOL_CFG_PATTERN5 () {0x200000;}' unless defined(&WOL_CFG_PATTERN5);
    eval 'sub WOL_CFG_PATTERN6 () {0x400000;}' unless defined(&WOL_CFG_PATTERN6);
    eval 'sub AGE_PATTERN_CFG0 () {0x14a4;}' unless defined(&AGE_PATTERN_CFG0);
    eval 'sub PATTERN_CFG_0_LEN_MASK () {0x7f;}' unless defined(&PATTERN_CFG_0_LEN_MASK);
    eval 'sub PATTERN_CFG_1_LEN_MASK () {0x7f00;}' unless defined(&PATTERN_CFG_1_LEN_MASK);
    eval 'sub PATTERN_CFG_2_LEN_MASK () {0x7f0000;}' unless defined(&PATTERN_CFG_2_LEN_MASK);
    eval 'sub PATTERN_CFG_3_LEN_MASK () {0x7f000000;}' unless defined(&PATTERN_CFG_3_LEN_MASK);
    eval 'sub AGE_PATTERN_CFG1 () {0x14a8;}' unless defined(&AGE_PATTERN_CFG1);
    eval 'sub PATTERN_CFG_4_LEN_MASK () {0x7f;}' unless defined(&PATTERN_CFG_4_LEN_MASK);
    eval 'sub PATTERN_CFG_5_LEN_MASK () {0x7f00;}' unless defined(&PATTERN_CFG_5_LEN_MASK);
    eval 'sub PATTERN_CFG_6_LEN_MASK () {0x7f0000;}' unless defined(&PATTERN_CFG_6_LEN_MASK);
    eval 'sub AGE_SRAM_RD_ADDR () {0x1500;}' unless defined(&AGE_SRAM_RD_ADDR);
    eval 'sub AGE_SRAM_RD_LEN () {0x1504;}' unless defined(&AGE_SRAM_RD_LEN);
    eval 'sub AGE_SRAM_RRD_ADDR () {0x1508;}' unless defined(&AGE_SRAM_RRD_ADDR);
    eval 'sub AGE_SRAM_RRD_LEN () {0x150c;}' unless defined(&AGE_SRAM_RRD_LEN);
    eval 'sub AGE_SRAM_TPD_ADDR () {0x1510;}' unless defined(&AGE_SRAM_TPD_ADDR);
    eval 'sub AGE_SRAM_TPD_LEN () {0x1514;}' unless defined(&AGE_SRAM_TPD_LEN);
    eval 'sub AGE_SRAM_TRD_ADDR () {0x1518;}' unless defined(&AGE_SRAM_TRD_ADDR);
    eval 'sub AGE_SRAM_TRD_LEN () {0x151c;}' unless defined(&AGE_SRAM_TRD_LEN);
    eval 'sub AGE_SRAM_RX_FIFO_ADDR () {0x1520;}' unless defined(&AGE_SRAM_RX_FIFO_ADDR);
    eval 'sub AGE_SRAM_RX_FIFO_LEN () {0x1524;}' unless defined(&AGE_SRAM_RX_FIFO_LEN);
    eval 'sub AGE_SRAM_TX_FIFO_ADDR () {0x1528;}' unless defined(&AGE_SRAM_TX_FIFO_ADDR);
    eval 'sub AGE_SRAM_TX_FIFO_LEN () {0x152c;}' unless defined(&AGE_SRAM_TX_FIFO_LEN);
    eval 'sub AGE_SRAM_TCPH_ADDR () {0x1530;}' unless defined(&AGE_SRAM_TCPH_ADDR);
    eval 'sub SRAM_TCPH_ADDR_MASK () {0xfff;}' unless defined(&SRAM_TCPH_ADDR_MASK);
    eval 'sub SRAM_PATH_ADDR_MASK () {0xfff0000;}' unless defined(&SRAM_PATH_ADDR_MASK);
    eval 'sub SRAM_TCPH_ADDR_SHIFT () {0;}' unless defined(&SRAM_TCPH_ADDR_SHIFT);
    eval 'sub SRAM_PATH_ADDR_SHIFT () {16;}' unless defined(&SRAM_PATH_ADDR_SHIFT);
    eval 'sub AGE_DMA_BLOCK () {0x1534;}' unless defined(&AGE_DMA_BLOCK);
    eval 'sub DMA_BLOCK_LOAD () {0x1;}' unless defined(&DMA_BLOCK_LOAD);
    eval 'sub AGE_DESC_ADDR_HI () {0x1540;}' unless defined(&AGE_DESC_ADDR_HI);
    eval 'sub AGE_DESC_RD_ADDR_LO () {0x1544;}' unless defined(&AGE_DESC_RD_ADDR_LO);
    eval 'sub AGE_DESC_RRD_ADDR_LO () {0x1548;}' unless defined(&AGE_DESC_RRD_ADDR_LO);
    eval 'sub AGE_DESC_TPD_ADDR_LO () {0x154c;}' unless defined(&AGE_DESC_TPD_ADDR_LO);
    eval 'sub AGE_DESC_CMB_ADDR_LO () {0x1550;}' unless defined(&AGE_DESC_CMB_ADDR_LO);
    eval 'sub AGE_DESC_SMB_ADDR_LO () {0x1554;}' unless defined(&AGE_DESC_SMB_ADDR_LO);
    eval 'sub AGE_DESC_RRD_RD_CNT () {0x1558;}' unless defined(&AGE_DESC_RRD_RD_CNT);
    eval 'sub DESC_RD_CNT_MASK () {0x7ff;}' unless defined(&DESC_RD_CNT_MASK);
    eval 'sub DESC_RRD_CNT_MASK () {0x7ff0000;}' unless defined(&DESC_RRD_CNT_MASK);
    eval 'sub DESC_RD_CNT_SHIFT () {0;}' unless defined(&DESC_RD_CNT_SHIFT);
    eval 'sub DESC_RRD_CNT_SHIFT () {16;}' unless defined(&DESC_RRD_CNT_SHIFT);
    eval 'sub AGE_DESC_TPD_CNT () {0x155c;}' unless defined(&AGE_DESC_TPD_CNT);
    eval 'sub DESC_TPD_CNT_MASK () {0x3ff;}' unless defined(&DESC_TPD_CNT_MASK);
    eval 'sub DESC_TPD_CNT_SHIFT () {0;}' unless defined(&DESC_TPD_CNT_SHIFT);
    eval 'sub AGE_TXQ_CFG () {0x1580;}' unless defined(&AGE_TXQ_CFG);
    eval 'sub TXQ_CFG_TPD_BURST_MASK () {0x1f;}' unless defined(&TXQ_CFG_TPD_BURST_MASK);
    eval 'sub TXQ_CFG_ENB () {0x20;}' unless defined(&TXQ_CFG_ENB);
    eval 'sub TXQ_CFG_ENHANCED_MODE () {0x40;}' unless defined(&TXQ_CFG_ENHANCED_MODE);
    eval 'sub TXQ_CFG_TPD_FETCH_THRESH_MASK () {0x3f00;}' unless defined(&TXQ_CFG_TPD_FETCH_THRESH_MASK);
    eval 'sub TXQ_CFG_TX_FIFO_BURST_MASK () {0xffff0000;}' unless defined(&TXQ_CFG_TX_FIFO_BURST_MASK);
    eval 'sub TXQ_CFG_TPD_BURST_SHIFT () {0;}' unless defined(&TXQ_CFG_TPD_BURST_SHIFT);
    eval 'sub TXQ_CFG_TPD_BURST_DEFAULT () {4;}' unless defined(&TXQ_CFG_TPD_BURST_DEFAULT);
    eval 'sub TXQ_CFG_TPD_FETCH_THRESH_SHIFT () {8;}' unless defined(&TXQ_CFG_TPD_FETCH_THRESH_SHIFT);
    eval 'sub TXQ_CFG_TPD_FETCH_DEFAULT () {16;}' unless defined(&TXQ_CFG_TPD_FETCH_DEFAULT);
    eval 'sub TXQ_CFG_TX_FIFO_BURST_SHIFT () {16;}' unless defined(&TXQ_CFG_TX_FIFO_BURST_SHIFT);
    eval 'sub TXQ_CFG_TX_FIFO_BURST_DEFAULT () {256;}' unless defined(&TXQ_CFG_TX_FIFO_BURST_DEFAULT);
    eval 'sub AGE_TX_JUMBO_TPD_TH_IPG () {0x1584;}' unless defined(&AGE_TX_JUMBO_TPD_TH_IPG);
    eval 'sub TX_JUMBO_TPD_TH_MASK () {0x7ff;}' unless defined(&TX_JUMBO_TPD_TH_MASK);
    eval 'sub TX_JUMBO_TPD_IPG_MASK () {0x1f0000;}' unless defined(&TX_JUMBO_TPD_IPG_MASK);
    eval 'sub TX_JUMBO_TPD_TH_SHIFT () {0;}' unless defined(&TX_JUMBO_TPD_TH_SHIFT);
    eval 'sub TX_JUMBO_TPD_IPG_SHIFT () {16;}' unless defined(&TX_JUMBO_TPD_IPG_SHIFT);
    eval 'sub TX_JUMBO_TPD_IPG_DEFAULT () {1;}' unless defined(&TX_JUMBO_TPD_IPG_DEFAULT);
    eval 'sub AGE_RXQ_CFG () {0x15a0;}' unless defined(&AGE_RXQ_CFG);
    eval 'sub RXQ_CFG_RD_BURST_MASK () {0xff;}' unless defined(&RXQ_CFG_RD_BURST_MASK);
    eval 'sub RXQ_CFG_RRD_BURST_THRESH_MASK () {0xff00;}' unless defined(&RXQ_CFG_RRD_BURST_THRESH_MASK);
    eval 'sub RXQ_CFG_RD_PREF_MIN_IPG_MASK () {0x1f0000;}' unless defined(&RXQ_CFG_RD_PREF_MIN_IPG_MASK);
    eval 'sub RXQ_CFG_CUT_THROUGH_ENB () {0x40000000;}' unless defined(&RXQ_CFG_CUT_THROUGH_ENB);
    eval 'sub RXQ_CFG_ENB () {0x80000000;}' unless defined(&RXQ_CFG_ENB);
    eval 'sub RXQ_CFG_RD_BURST_SHIFT () {0;}' unless defined(&RXQ_CFG_RD_BURST_SHIFT);
    eval 'sub RXQ_CFG_RD_BURST_DEFAULT () {8;}' unless defined(&RXQ_CFG_RD_BURST_DEFAULT);
    eval 'sub RXQ_CFG_RRD_BURST_THRESH_SHIFT () {8;}' unless defined(&RXQ_CFG_RRD_BURST_THRESH_SHIFT);
    eval 'sub RXQ_CFG_RRD_BURST_THRESH_DEFAULT () {8;}' unless defined(&RXQ_CFG_RRD_BURST_THRESH_DEFAULT);
    eval 'sub RXQ_CFG_RD_PREF_MIN_IPG_SHIFT () {16;}' unless defined(&RXQ_CFG_RD_PREF_MIN_IPG_SHIFT);
    eval 'sub RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT () {1;}' unless defined(&RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT);
    eval 'sub AGE_RXQ_JUMBO_CFG () {0x15a4;}' unless defined(&AGE_RXQ_JUMBO_CFG);
    eval 'sub RXQ_JUMBO_CFG_SZ_THRESH_MASK () {0x7ff;}' unless defined(&RXQ_JUMBO_CFG_SZ_THRESH_MASK);
    eval 'sub RXQ_JUMBO_CFG_LKAH_MASK () {0x7800;}' unless defined(&RXQ_JUMBO_CFG_LKAH_MASK);
    eval 'sub RXQ_JUMBO_CFG_RRD_TIMER_MASK () {0xffff0000;}' unless defined(&RXQ_JUMBO_CFG_RRD_TIMER_MASK);
    eval 'sub RXQ_JUMBO_CFG_SZ_THRESH_SHIFT () {0;}' unless defined(&RXQ_JUMBO_CFG_SZ_THRESH_SHIFT);
    eval 'sub RXQ_JUMBO_CFG_LKAH_SHIFT () {11;}' unless defined(&RXQ_JUMBO_CFG_LKAH_SHIFT);
    eval 'sub RXQ_JUMBO_CFG_LKAH_DEFAULT () {0x1;}' unless defined(&RXQ_JUMBO_CFG_LKAH_DEFAULT);
    eval 'sub RXQ_JUMBO_CFG_RRD_TIMER_SHIFT () {16;}' unless defined(&RXQ_JUMBO_CFG_RRD_TIMER_SHIFT);
    eval 'sub AGE_RXQ_FIFO_PAUSE_THRESH () {0x15a8;}' unless defined(&AGE_RXQ_FIFO_PAUSE_THRESH);
    eval 'sub RXQ_FIFO_PAUSE_THRESH_LO_MASK () {0xfff;}' unless defined(&RXQ_FIFO_PAUSE_THRESH_LO_MASK);
    eval 'sub RXQ_FIFO_PAUSE_THRESH_HI_MASK () {0xfff000;}' unless defined(&RXQ_FIFO_PAUSE_THRESH_HI_MASK);
    eval 'sub RXQ_FIFO_PAUSE_THRESH_LO_SHIFT () {0;}' unless defined(&RXQ_FIFO_PAUSE_THRESH_LO_SHIFT);
    eval 'sub RXQ_FIFO_PAUSE_THRESH_HI_SHIFT () {16;}' unless defined(&RXQ_FIFO_PAUSE_THRESH_HI_SHIFT);
    eval 'sub AGE_RXQ_RRD_PAUSE_THRESH () {0x15ac;}' unless defined(&AGE_RXQ_RRD_PAUSE_THRESH);
    eval 'sub RXQ_RRD_PAUSE_THRESH_HI_MASK () {0xfff;}' unless defined(&RXQ_RRD_PAUSE_THRESH_HI_MASK);
    eval 'sub RXQ_RRD_PAUSE_THRESH_LO_MASK () {0xfff0000;}' unless defined(&RXQ_RRD_PAUSE_THRESH_LO_MASK);
    eval 'sub RXQ_RRD_PAUSE_THRESH_HI_SHIFT () {0;}' unless defined(&RXQ_RRD_PAUSE_THRESH_HI_SHIFT);
    eval 'sub RXQ_RRD_PAUSE_THRESH_LO_SHIFT () {16;}' unless defined(&RXQ_RRD_PAUSE_THRESH_LO_SHIFT);
    eval 'sub AGE_DMA_CFG () {0x15c0;}' unless defined(&AGE_DMA_CFG);
    eval 'sub DMA_CFG_IN_ORDER () {0x1;}' unless defined(&DMA_CFG_IN_ORDER);
    eval 'sub DMA_CFG_ENH_ORDER () {0x2;}' unless defined(&DMA_CFG_ENH_ORDER);
    eval 'sub DMA_CFG_OUT_ORDER () {0x4;}' unless defined(&DMA_CFG_OUT_ORDER);
    eval 'sub DMA_CFG_RCB_64 () {0x;}' unless defined(&DMA_CFG_RCB_64);
    eval 'sub DMA_CFG_RCB_128 () {0x8;}' unless defined(&DMA_CFG_RCB_128);
    eval 'sub DMA_CFG_RD_BURST_128 () {0x;}' unless defined(&DMA_CFG_RD_BURST_128);
    eval 'sub DMA_CFG_RD_BURST_256 () {0x10;}' unless defined(&DMA_CFG_RD_BURST_256);
    eval 'sub DMA_CFG_RD_BURST_512 () {0x20;}' unless defined(&DMA_CFG_RD_BURST_512);
    eval 'sub DMA_CFG_RD_BURST_1024 () {0x30;}' unless defined(&DMA_CFG_RD_BURST_1024);
    eval 'sub DMA_CFG_RD_BURST_2048 () {0x40;}' unless defined(&DMA_CFG_RD_BURST_2048);
    eval 'sub DMA_CFG_RD_BURST_4096 () {0x50;}' unless defined(&DMA_CFG_RD_BURST_4096);
    eval 'sub DMA_CFG_WR_BURST_128 () {0x;}' unless defined(&DMA_CFG_WR_BURST_128);
    eval 'sub DMA_CFG_WR_BURST_256 () {0x80;}' unless defined(&DMA_CFG_WR_BURST_256);
    eval 'sub DMA_CFG_WR_BURST_512 () {0x100;}' unless defined(&DMA_CFG_WR_BURST_512);
    eval 'sub DMA_CFG_WR_BURST_1024 () {0x180;}' unless defined(&DMA_CFG_WR_BURST_1024);
    eval 'sub DMA_CFG_WR_BURST_2048 () {0x200;}' unless defined(&DMA_CFG_WR_BURST_2048);
    eval 'sub DMA_CFG_WR_BURST_4096 () {0x280;}' unless defined(&DMA_CFG_WR_BURST_4096);
    eval 'sub DMA_CFG_RD_ENB () {0x400;}' unless defined(&DMA_CFG_RD_ENB);
    eval 'sub DMA_CFG_WR_ENB () {0x800;}' unless defined(&DMA_CFG_WR_ENB);
    eval 'sub DMA_CFG_RD_BURST_MASK () {0x7;}' unless defined(&DMA_CFG_RD_BURST_MASK);
    eval 'sub DMA_CFG_RD_BURST_SHIFT () {4;}' unless defined(&DMA_CFG_RD_BURST_SHIFT);
    eval 'sub DMA_CFG_WR_BURST_MASK () {0x7;}' unless defined(&DMA_CFG_WR_BURST_MASK);
    eval 'sub DMA_CFG_WR_BURST_SHIFT () {7;}' unless defined(&DMA_CFG_WR_BURST_SHIFT);
    eval 'sub AGE_CSMB_CTRL () {0x15d0;}' unless defined(&AGE_CSMB_CTRL);
    eval 'sub CSMB_CTRL_CMB_KICK () {0x1;}' unless defined(&CSMB_CTRL_CMB_KICK);
    eval 'sub CSMB_CTRL_SMB_KICK () {0x2;}' unless defined(&CSMB_CTRL_SMB_KICK);
    eval 'sub CSMB_CTRL_CMB_ENB () {0x4;}' unless defined(&CSMB_CTRL_CMB_ENB);
    eval 'sub CSMB_CTRL_SMB_ENB () {0x8;}' unless defined(&CSMB_CTRL_SMB_ENB);
    eval 'sub AGE_CMB_WR_THRESH () {0x15d4;}' unless defined(&AGE_CMB_WR_THRESH);
    eval 'sub CMB_WR_THRESH_RRD_MASK () {0x7ff;}' unless defined(&CMB_WR_THRESH_RRD_MASK);
    eval 'sub CMB_WR_THRESH_TPD_MASK () {0x7ff0000;}' unless defined(&CMB_WR_THRESH_TPD_MASK);
    eval 'sub CMB_WR_THRESH_RRD_SHIFT () {0;}' unless defined(&CMB_WR_THRESH_RRD_SHIFT);
    eval 'sub CMB_WR_THRESH_RRD_DEFAULT () {4;}' unless defined(&CMB_WR_THRESH_RRD_DEFAULT);
    eval 'sub CMB_WR_THRESH_TPD_SHIFT () {16;}' unless defined(&CMB_WR_THRESH_TPD_SHIFT);
    eval 'sub CMB_WR_THRESH_TPD_DEFAULT () {4;}' unless defined(&CMB_WR_THRESH_TPD_DEFAULT);
    eval 'sub AGE_CMB_WR_TIMER () {0x15d8;}' unless defined(&AGE_CMB_WR_TIMER);
    eval 'sub CMB_WR_TIMER_RX_MASK () {0xffff;}' unless defined(&CMB_WR_TIMER_RX_MASK);
    eval 'sub CMB_WR_TIMER_TX_MASK () {0xffff0000;}' unless defined(&CMB_WR_TIMER_TX_MASK);
    eval 'sub CMB_WR_TIMER_RX_SHIFT () {0;}' unless defined(&CMB_WR_TIMER_RX_SHIFT);
    eval 'sub CMB_WR_TIMER_TX_SHIFT () {16;}' unless defined(&CMB_WR_TIMER_TX_SHIFT);
    eval 'sub AGE_CMB_RX_PKT_CNT () {0x15dc;}' unless defined(&AGE_CMB_RX_PKT_CNT);
    eval 'sub AGE_CMB_TX_PKT_CNT () {0x15e0;}' unless defined(&AGE_CMB_TX_PKT_CNT);
    eval 'sub AGE_SMB_TIMER () {0x15e4;}' unless defined(&AGE_SMB_TIMER);
    eval 'sub AGE_MBOX () {0x15f0;}' unless defined(&AGE_MBOX);
    eval 'sub MBOX_RD_PROD_IDX_MASK () {0x7ff;}' unless defined(&MBOX_RD_PROD_IDX_MASK);
    eval 'sub MBOX_RRD_CONS_IDX_MASK () {0x3ff800;}' unless defined(&MBOX_RRD_CONS_IDX_MASK);
    eval 'sub MBOX_TD_PROD_IDX_MASK () {0xffc00000;}' unless defined(&MBOX_TD_PROD_IDX_MASK);
    eval 'sub MBOX_RD_PROD_IDX_SHIFT () {0;}' unless defined(&MBOX_RD_PROD_IDX_SHIFT);
    eval 'sub MBOX_RRD_CONS_IDX_SHIFT () {11;}' unless defined(&MBOX_RRD_CONS_IDX_SHIFT);
    eval 'sub MBOX_TD_PROD_IDX_SHIFT () {22;}' unless defined(&MBOX_TD_PROD_IDX_SHIFT);
    eval 'sub AGE_INTR_STATUS () {0x1600;}' unless defined(&AGE_INTR_STATUS);
    eval 'sub INTR_SMB () {0x1;}' unless defined(&INTR_SMB);
    eval 'sub INTR_MOD_TIMER () {0x2;}' unless defined(&INTR_MOD_TIMER);
    eval 'sub INTR_MANUAL_TIMER () {0x4;}' unless defined(&INTR_MANUAL_TIMER);
    eval 'sub INTR_RX_FIFO_OFLOW () {0x8;}' unless defined(&INTR_RX_FIFO_OFLOW);
    eval 'sub INTR_RD_UNDERRUN () {0x10;}' unless defined(&INTR_RD_UNDERRUN);
    eval 'sub INTR_RRD_OFLOW () {0x20;}' unless defined(&INTR_RRD_OFLOW);
    eval 'sub INTR_TX_FIFO_UNDERRUN () {0x40;}' unless defined(&INTR_TX_FIFO_UNDERRUN);
    eval 'sub INTR_LINK_CHG () {0x80;}' unless defined(&INTR_LINK_CHG);
    eval 'sub INTR_HOST_RD_UNDERRUN () {0x100;}' unless defined(&INTR_HOST_RD_UNDERRUN);
    eval 'sub INTR_HOST_RRD_OFLOW () {0x200;}' unless defined(&INTR_HOST_RRD_OFLOW);
    eval 'sub INTR_DMA_RD_TO_RST () {0x400;}' unless defined(&INTR_DMA_RD_TO_RST);
    eval 'sub INTR_DMA_WR_TO_RST () {0x800;}' unless defined(&INTR_DMA_WR_TO_RST);
    eval 'sub INTR_GPHY () {0x1000;}' unless defined(&INTR_GPHY);
    eval 'sub INTR_RX_PKT () {0x10000;}' unless defined(&INTR_RX_PKT);
    eval 'sub INTR_TX_PKT () {0x20000;}' unless defined(&INTR_TX_PKT);
    eval 'sub INTR_TX_DMA () {0x40000;}' unless defined(&INTR_TX_DMA);
    eval 'sub INTR_RX_DMA () {0x80000;}' unless defined(&INTR_RX_DMA);
    eval 'sub INTR_CMB_RX () {0x100000;}' unless defined(&INTR_CMB_RX);
    eval 'sub INTR_CMB_TX () {0x200000;}' unless defined(&INTR_CMB_TX);
    eval 'sub INTR_MAC_RX () {0x400000;}' unless defined(&INTR_MAC_RX);
    eval 'sub INTR_MAC_TX () {0x800000;}' unless defined(&INTR_MAC_TX);
    eval 'sub INTR_UNDERRUN () {0x1000000;}' unless defined(&INTR_UNDERRUN);
    eval 'sub INTR_FRAME_ERROR () {0x2000000;}' unless defined(&INTR_FRAME_ERROR);
    eval 'sub INTR_FRAME_OK () {0x4000000;}' unless defined(&INTR_FRAME_OK);
    eval 'sub INTR_CSUM_ERROR () {0x8000000;}' unless defined(&INTR_CSUM_ERROR);
    eval 'sub INTR_PHY_LINK_DOWN () {0x10000000;}' unless defined(&INTR_PHY_LINK_DOWN);
    eval 'sub INTR_DIS_SMB () {0x20000000;}' unless defined(&INTR_DIS_SMB);
    eval 'sub INTR_DIS_DMA () {0x40000000;}' unless defined(&INTR_DIS_DMA);
    eval 'sub INTR_DIS_INT () {0x80000000;}' unless defined(&INTR_DIS_INT);
    eval 'sub AGE_INTR_MASK () {0x1604;}' unless defined(&AGE_INTR_MASK);
    eval 'sub AGE_INTRS () {( &INTR_SMB |  &INTR_DMA_RD_TO_RST |  &INTR_DMA_WR_TO_RST |  &INTR_CMB_TX |  &INTR_CMB_RX);}' unless defined(&AGE_INTRS);
    eval 'sub RRD_PROD_MASK () {0xffff;}' unless defined(&RRD_PROD_MASK);
    eval 'sub RD_CONS_MASK () {0xffff0000;}' unless defined(&RD_CONS_MASK);
    eval 'sub RRD_PROD_SHIFT () {0;}' unless defined(&RRD_PROD_SHIFT);
    eval 'sub RD_CONS_SHIFT () {16;}' unless defined(&RD_CONS_SHIFT);
    eval 'sub CMB_UPDATED () {0x1;}' unless defined(&CMB_UPDATED);
    eval 'sub TPD_CONS_MASK () {0xffff0000;}' unless defined(&TPD_CONS_MASK);
    eval 'sub TPD_CONS_SHIFT () {16;}' unless defined(&TPD_CONS_SHIFT);
    eval 'sub AGE_RRD_NSEGS_MASK () {0xff;}' unless defined(&AGE_RRD_NSEGS_MASK);
    eval 'sub AGE_RRD_CONS_MASK () {0xffff0000;}' unless defined(&AGE_RRD_CONS_MASK);
    eval 'sub AGE_RRD_NSEGS_SHIFT () {0;}' unless defined(&AGE_RRD_NSEGS_SHIFT);
    eval 'sub AGE_RRD_CONS_SHIFT () {16;}' unless defined(&AGE_RRD_CONS_SHIFT);
    eval 'sub AGE_RRD_CSUM_MASK () {0xffff;}' unless defined(&AGE_RRD_CSUM_MASK);
    eval 'sub AGE_RRD_LEN_MASK () {0xffff0000;}' unless defined(&AGE_RRD_LEN_MASK);
    eval 'sub AGE_RRD_CSUM_SHIFT () {0;}' unless defined(&AGE_RRD_CSUM_SHIFT);
    eval 'sub AGE_RRD_LEN_SHIFT () {16;}' unless defined(&AGE_RRD_LEN_SHIFT);
    eval 'sub AGE_RRD_ETHERNET () {0x80;}' unless defined(&AGE_RRD_ETHERNET);
    eval 'sub AGE_RRD_VLAN () {0x100;}' unless defined(&AGE_RRD_VLAN);
    eval 'sub AGE_RRD_ERROR () {0x200;}' unless defined(&AGE_RRD_ERROR);
    eval 'sub AGE_RRD_IPV4 () {0x400;}' unless defined(&AGE_RRD_IPV4);
    eval 'sub AGE_RRD_UDP () {0x800;}' unless defined(&AGE_RRD_UDP);
    eval 'sub AGE_RRD_TCP () {0x1000;}' unless defined(&AGE_RRD_TCP);
    eval 'sub AGE_RRD_BCAST () {0x2000;}' unless defined(&AGE_RRD_BCAST);
    eval 'sub AGE_RRD_MCAST () {0x4000;}' unless defined(&AGE_RRD_MCAST);
    eval 'sub AGE_RRD_PAUSE () {0x8000;}' unless defined(&AGE_RRD_PAUSE);
    eval 'sub AGE_RRD_CRC () {0x10000;}' unless defined(&AGE_RRD_CRC);
    eval 'sub AGE_RRD_CODE () {0x20000;}' unless defined(&AGE_RRD_CODE);
    eval 'sub AGE_RRD_DRIBBLE () {0x40000;}' unless defined(&AGE_RRD_DRIBBLE);
    eval 'sub AGE_RRD_RUNT () {0x80000;}' unless defined(&AGE_RRD_RUNT);
    eval 'sub AGE_RRD_OFLOW () {0x100000;}' unless defined(&AGE_RRD_OFLOW);
    eval 'sub AGE_RRD_TRUNC () {0x200000;}' unless defined(&AGE_RRD_TRUNC);
    eval 'sub AGE_RRD_IPCSUM_NOK () {0x400000;}' unless defined(&AGE_RRD_IPCSUM_NOK);
    eval 'sub AGE_RRD_TCP_UDPCSUM_NOK () {0x800000;}' unless defined(&AGE_RRD_TCP_UDPCSUM_NOK);
    eval 'sub AGE_RRD_LENGTH_NOK () {0x1000000;}' unless defined(&AGE_RRD_LENGTH_NOK);
    eval 'sub AGE_RRD_DES_ADDR_FILTERED () {0x2000000;}' unless defined(&AGE_RRD_DES_ADDR_FILTERED);
    eval 'sub AGE_RRD_VLAN_MASK () {0xffff0000;}' unless defined(&AGE_RRD_VLAN_MASK);
    eval 'sub AGE_RRD_VLAN_SHIFT () {16;}' unless defined(&AGE_RRD_VLAN_SHIFT);
    eval 'sub AGE_RX_NSEGS {
        my($x) = @_;
	    eval q(((($x) &  &AGE_RRD_NSEGS_MASK) >>  &AGE_RRD_NSEGS_SHIFT));
    }' unless defined(&AGE_RX_NSEGS);
    eval 'sub AGE_RX_CONS {
        my($x) = @_;
	    eval q(((($x) &  &AGE_RRD_CONS_MASK) >>  &AGE_RRD_CONS_SHIFT));
    }' unless defined(&AGE_RX_CONS);
    eval 'sub AGE_RX_CSUM {
        my($x) = @_;
	    eval q(((($x) &  &AGE_RRD_CSUM_MASK) >>  &AGE_RRD_CSUM_SHIFT));
    }' unless defined(&AGE_RX_CSUM);
    eval 'sub AGE_RX_BYTES {
        my($x) = @_;
	    eval q(((($x) &  &AGE_RRD_LEN_MASK) >>  &AGE_RRD_LEN_SHIFT));
    }' unless defined(&AGE_RX_BYTES);
    eval 'sub AGE_RX_VLAN {
        my($x) = @_;
	    eval q(((($x) &  &AGE_RRD_VLAN_MASK) >>  &AGE_RRD_VLAN_SHIFT));
    }' unless defined(&AGE_RX_VLAN);
    eval 'sub AGE_RX_VLAN_TAG {
        my($x) = @_;
	    eval q(((($x) >> 4) | ((($x) & 7) << 13) | ((($x) & 8) << 9)));
    }' unless defined(&AGE_RX_VLAN_TAG);
    eval 'sub AGE_RD_LEN_MASK () {0xffff;}' unless defined(&AGE_RD_LEN_MASK);
    eval 'sub AGE_CONS_UPD_REQ_MASK () {0xffff0000;}' unless defined(&AGE_CONS_UPD_REQ_MASK);
    eval 'sub AGE_RD_LEN_SHIFT () {0;}' unless defined(&AGE_RD_LEN_SHIFT);
    eval 'sub AGE_CONS_UPD_REQ_SHIFT () {16;}' unless defined(&AGE_CONS_UPD_REQ_SHIFT);
    eval 'sub AGE_TD_VLAN_MASK () {0xffff0000;}' unless defined(&AGE_TD_VLAN_MASK);
    eval 'sub AGE_TD_PKT_INT () {0x8000;}' unless defined(&AGE_TD_PKT_INT);
    eval 'sub AGE_TD_DMA_INT () {0x4000;}' unless defined(&AGE_TD_DMA_INT);
    eval 'sub AGE_TD_BUFLEN_MASK () {0x3fff;}' unless defined(&AGE_TD_BUFLEN_MASK);
    eval 'sub AGE_TD_VLAN_SHIFT () {16;}' unless defined(&AGE_TD_VLAN_SHIFT);
    eval 'sub AGE_TX_VLAN_TAG {
        my($x) = @_;
	    eval q(((($x) << 4) | (($x) >> 13) | ((($x) >> 9) & 8)));
    }' unless defined(&AGE_TX_VLAN_TAG);
    eval 'sub AGE_TD_BUFLEN_SHIFT () {0;}' unless defined(&AGE_TD_BUFLEN_SHIFT);
    eval 'sub AGE_TX_BYTES {
        my($x) = @_;
	    eval q(((($x) <<  &AGE_TD_BUFLEN_SHIFT) &  &AGE_TD_BUFLEN_MASK));
    }' unless defined(&AGE_TX_BYTES);
    eval 'sub AGE_TD_TSO_MSS () {0xfff80000;}' unless defined(&AGE_TD_TSO_MSS);
    eval 'sub AGE_TD_TSO_HDR () {0x40000;}' unless defined(&AGE_TD_TSO_HDR);
    eval 'sub AGE_TD_TSO_TCPHDR_LEN () {0x3c000;}' unless defined(&AGE_TD_TSO_TCPHDR_LEN);
    eval 'sub AGE_TD_IPHDR_LEN () {0x3c00;}' unless defined(&AGE_TD_IPHDR_LEN);
    eval 'sub AGE_TD_LLC_SNAP () {0x200;}' unless defined(&AGE_TD_LLC_SNAP);
    eval 'sub AGE_TD_VLAN_TAGGED () {0x100;}' unless defined(&AGE_TD_VLAN_TAGGED);
    eval 'sub AGE_TD_UDPCSUM () {0x80;}' unless defined(&AGE_TD_UDPCSUM);
    eval 'sub AGE_TD_TCPCSUM () {0x40;}' unless defined(&AGE_TD_TCPCSUM);
    eval 'sub AGE_TD_IPCSUM () {0x20;}' unless defined(&AGE_TD_IPCSUM);
    eval 'sub AGE_TD_TSO_IPV4 () {0x10;}' unless defined(&AGE_TD_TSO_IPV4);
    eval 'sub AGE_TD_TSO_IPV6 () {0x12;}' unless defined(&AGE_TD_TSO_IPV6);
    eval 'sub AGE_TD_CSUM () {0x8;}' unless defined(&AGE_TD_CSUM);
    eval 'sub AGE_TD_INSERT_VLAN_TAG () {0x4;}' unless defined(&AGE_TD_INSERT_VLAN_TAG);
    eval 'sub AGE_TD_COALESCE () {0x2;}' unless defined(&AGE_TD_COALESCE);
    eval 'sub AGE_TD_EOP () {0x1;}' unless defined(&AGE_TD_EOP);
    eval 'sub AGE_TD_CSUM_PLOADOFFSET () {0xff0000;}' unless defined(&AGE_TD_CSUM_PLOADOFFSET);
    eval 'sub AGE_TD_CSUM_XSUMOFFSET () {0xff000000;}' unless defined(&AGE_TD_CSUM_XSUMOFFSET);
    eval 'sub AGE_TD_CSUM_XSUMOFFSET_SHIFT () {24;}' unless defined(&AGE_TD_CSUM_XSUMOFFSET_SHIFT);
    eval 'sub AGE_TD_CSUM_PLOADOFFSET_SHIFT () {16;}' unless defined(&AGE_TD_CSUM_PLOADOFFSET_SHIFT);
    eval 'sub AGE_TD_TSO_MSS_SHIFT () {19;}' unless defined(&AGE_TD_TSO_MSS_SHIFT);
    eval 'sub AGE_TD_TSO_TCPHDR_LEN_SHIFT () {14;}' unless defined(&AGE_TD_TSO_TCPHDR_LEN_SHIFT);
    eval 'sub AGE_TD_IPHDR_LEN_SHIFT () {10;}' unless defined(&AGE_TD_IPHDR_LEN_SHIFT);
    eval 'sub AGE_TX_RING_CNT () {256;}' unless defined(&AGE_TX_RING_CNT);
    eval 'sub AGE_RX_RING_CNT () {256;}' unless defined(&AGE_RX_RING_CNT);
    eval 'sub AGE_RR_RING_CNT () {( &AGE_TX_RING_CNT +  &AGE_RX_RING_CNT);}' unless defined(&AGE_RR_RING_CNT);
    eval 'sub AGE_TX_RING_ALIGN () {16;}' unless defined(&AGE_TX_RING_ALIGN);
    eval 'sub AGE_RX_RING_ALIGN () {16;}' unless defined(&AGE_RX_RING_ALIGN);
    eval 'sub AGE_RR_RING_ALIGN () {16;}' unless defined(&AGE_RR_RING_ALIGN);
    eval 'sub AGE_CMB_ALIGN () {16;}' unless defined(&AGE_CMB_ALIGN);
    eval 'sub AGE_SMB_ALIGN () {16;}' unless defined(&AGE_SMB_ALIGN);
    eval 'sub AGE_TSO_MAXSEGSIZE () {4096;}' unless defined(&AGE_TSO_MAXSEGSIZE);
    eval 'sub AGE_TSO_MAXSIZE () {(65535+ $sizeof{\'struct ether_vlan_header\'});}' unless defined(&AGE_TSO_MAXSIZE);
    eval 'sub AGE_MAXTXSEGS () {32;}' unless defined(&AGE_MAXTXSEGS);
    eval 'sub AGE_ADDR_LO {
        my($x) = @_;
	    eval q((( &uint64_t) ($x) & 0xffffffff));
    }' unless defined(&AGE_ADDR_LO);
    eval 'sub AGE_ADDR_HI {
        my($x) = @_;
	    eval q((( &uint64_t) ($x) >> 32));
    }' unless defined(&AGE_ADDR_HI);
    eval 'sub AGE_MSI_MESSAGES () {1;}' unless defined(&AGE_MSI_MESSAGES);
    eval 'sub AGE_MSIX_MESSAGES () {1;}' unless defined(&AGE_MSIX_MESSAGES);
    eval 'sub AGE_JUMBO_FRAMELEN () {10240;}' unless defined(&AGE_JUMBO_FRAMELEN);
    eval 'sub AGE_JUMBO_MTU () {( &AGE_JUMBO_FRAMELEN -  &EVL_ENCAPLEN -  &ETHER_HDR_LEN -  &ETHER_CRC_LEN);}' unless defined(&AGE_JUMBO_MTU);
    eval 'sub AGE_DESC_INC {
        my($x, $y) = @_;
	    eval q((($x) = (($x) + 1) % ($y)));
    }' unless defined(&AGE_DESC_INC);
    eval 'sub AGE_PROC_MIN () {30;}' unless defined(&AGE_PROC_MIN);
    eval 'sub AGE_PROC_MAX () {( &AGE_RX_RING_CNT - 1);}' unless defined(&AGE_PROC_MAX);
    eval 'sub AGE_PROC_DEFAULT () {( &AGE_RX_RING_CNT / 2);}' unless defined(&AGE_PROC_DEFAULT);
    eval 'sub AGE_TX_RING_SZ () {($sizeof{\'struct tx_desc\'} *  &AGE_TX_RING_CNT);}' unless defined(&AGE_TX_RING_SZ);
    eval 'sub AGE_RX_RING_SZ () {($sizeof{\'struct rx_desc\'} *  &AGE_RX_RING_CNT);}' unless defined(&AGE_RX_RING_SZ);
    eval 'sub AGE_RR_RING_SZ () {($sizeof{\'struct rx_rdesc\'} *  &AGE_RR_RING_CNT);}' unless defined(&AGE_RR_RING_SZ);
    eval 'sub AGE_CMB_BLOCK_SZ () {$sizeof{\'struct cmb\'};}' unless defined(&AGE_CMB_BLOCK_SZ);
    eval 'sub AGE_SMB_BLOCK_SZ () {$sizeof{\'struct smb\'};}' unless defined(&AGE_SMB_BLOCK_SZ);
    eval 'sub AGE_FLAG_PCIE () {0x1;}' unless defined(&AGE_FLAG_PCIE);
    eval 'sub AGE_FLAG_PCIX () {0x2;}' unless defined(&AGE_FLAG_PCIX);
    eval 'sub AGE_FLAG_MSI () {0x4;}' unless defined(&AGE_FLAG_MSI);
    eval 'sub AGE_FLAG_MSIX () {0x8;}' unless defined(&AGE_FLAG_MSIX);
    eval 'sub AGE_FLAG_PMCAP () {0x10;}' unless defined(&AGE_FLAG_PMCAP);
    eval 'sub AGE_FLAG_DETACH () {0x4000;}' unless defined(&AGE_FLAG_DETACH);
    eval 'sub AGE_FLAG_LINK () {0x8000;}' unless defined(&AGE_FLAG_LINK);
    eval 'sub CSR_WRITE_4 {
        my($sc, $reg, $val) = @_;
	    eval q( &bus_space_write_4(($sc)-> &sc_mem_bt, ($sc)-> &sc_mem_bh, ($reg), ($val)));
    }' unless defined(&CSR_WRITE_4);
    eval 'sub CSR_WRITE_2 {
        my($sc, $reg, $val) = @_;
	    eval q( &bus_space_write_2(($sc)-> &sc_mem_bt, ($sc)-> &sc_mem_bh, ($reg), ($val)));
    }' unless defined(&CSR_WRITE_2);
    eval 'sub CSR_READ_2 {
        my($sc, $reg) = @_;
	    eval q( &bus_space_read_2(($sc)-> &sc_mem_bt, ($sc)-> &sc_mem_bh, ($reg)));
    }' unless defined(&CSR_READ_2);
    eval 'sub CSR_READ_4 {
        my($sc, $reg) = @_;
	    eval q( &bus_space_read_4(($sc)-> &sc_mem_bt, ($sc)-> &sc_mem_bh, ($reg)));
    }' unless defined(&CSR_READ_4);
    eval 'sub AGE_COMMIT_MBOX {
        my($_sc) = @_;
	    eval q( &do {  &CSR_WRITE_4($_sc,  &AGE_MBOX, ((($_sc)-> ($age_cdata->{age_rx_cons}) <<  &MBOX_RD_PROD_IDX_SHIFT) &  &MBOX_RD_PROD_IDX_MASK) | ((($_sc)-> ($age_cdata->{age_rr_cons}) <<  &MBOX_RRD_CONS_IDX_SHIFT) &  &MBOX_RRD_CONS_IDX_MASK) | ((($_sc)-> ($age_cdata->{age_tx_prod}) <<  &MBOX_TD_PROD_IDX_SHIFT) &  &MBOX_TD_PROD_IDX_MASK)); }  &while (0));
    }' unless defined(&AGE_COMMIT_MBOX);
    eval 'sub AGE_RXCHAIN_RESET {
        my($_sc) = @_;
	    eval q( &do { ($_sc)-> ($age_cdata->{age_rxhead}) =  &NULL; ($_sc)-> ($age_cdata->{age_rxtail}) =  &NULL; ($_sc)-> ($age_cdata->{age_rxprev_tail}) =  &NULL; ($_sc)-> ($age_cdata->{age_rxlen}) = 0; }  &while (0));
    }' unless defined(&AGE_RXCHAIN_RESET);
    eval 'sub AGE_TX_TIMEOUT () {5;}' unless defined(&AGE_TX_TIMEOUT);
    eval 'sub AGE_RESET_TIMEOUT () {100;}' unless defined(&AGE_RESET_TIMEOUT);
    eval 'sub AGE_TIMEOUT () {1000;}' unless defined(&AGE_TIMEOUT);
    eval 'sub AGE_PHY_TIMEOUT () {1000;}' unless defined(&AGE_PHY_TIMEOUT);
}
1;
