require '_h2ph_pre.ph';

no warnings qw(redefine misc);

unless(defined(&_IF_ALEREG_H)) {
    eval 'sub _IF_ALEREG_H () {1;}' unless defined(&_IF_ALEREG_H);
    eval 'sub ALE_PCIR_BAR () {0x10;}' unless defined(&ALE_PCIR_BAR);
    eval 'sub ALE_SPI_CTRL () {0x200;}' unless defined(&ALE_SPI_CTRL);
    eval 'sub SPI_VPD_ENB () {0x2000;}' unless defined(&SPI_VPD_ENB);
    eval 'sub ALE_SPI_ADDR () {0x204;}' unless defined(&ALE_SPI_ADDR);
    eval 'sub ALE_SPI_DATA () {0x208;}' unless defined(&ALE_SPI_DATA);
    eval 'sub ALE_SPI_CONFIG () {0x20c;}' unless defined(&ALE_SPI_CONFIG);
    eval 'sub ALE_SPI_OP_PROGRAM () {0x210;}' unless defined(&ALE_SPI_OP_PROGRAM);
    eval 'sub ALE_SPI_OP_SC_ERASE () {0x211;}' unless defined(&ALE_SPI_OP_SC_ERASE);
    eval 'sub ALE_SPI_OP_CHIP_ERASE () {0x212;}' unless defined(&ALE_SPI_OP_CHIP_ERASE);
    eval 'sub ALE_SPI_OP_RDID () {0x213;}' unless defined(&ALE_SPI_OP_RDID);
    eval 'sub ALE_SPI_OP_WREN () {0x214;}' unless defined(&ALE_SPI_OP_WREN);
    eval 'sub ALE_SPI_OP_RDSR () {0x215;}' unless defined(&ALE_SPI_OP_RDSR);
    eval 'sub ALE_SPI_OP_WRSR () {0x216;}' unless defined(&ALE_SPI_OP_WRSR);
    eval 'sub ALE_SPI_OP_READ () {0x217;}' unless defined(&ALE_SPI_OP_READ);
    eval 'sub ALE_TWSI_CTRL () {0x218;}' unless defined(&ALE_TWSI_CTRL);
    eval 'sub TWSI_CTRL_SW_LD_START () {0x800;}' unless defined(&TWSI_CTRL_SW_LD_START);
    eval 'sub TWSI_CTRL_HW_LD_START () {0x1000;}' unless defined(&TWSI_CTRL_HW_LD_START);
    eval 'sub TWSI_CTRL_LD_EXIST () {0x400000;}' unless defined(&TWSI_CTRL_LD_EXIST);
    eval 'sub ALE_DEV_MISC_CTRL () {0x21c;}' unless defined(&ALE_DEV_MISC_CTRL);
    eval 'sub ALE_PCIE_PHYMISC () {0x1000;}' unless defined(&ALE_PCIE_PHYMISC);
    eval 'sub PCIE_PHYMISC_FORCE_RCV_DET () {0x4;}' unless defined(&PCIE_PHYMISC_FORCE_RCV_DET);
    eval 'sub ALE_MASTER_CFG () {0x1400;}' unless defined(&ALE_MASTER_CFG);
    eval 'sub MASTER_RESET () {0x1;}' unless defined(&MASTER_RESET);
    eval 'sub MASTER_MTIMER_ENB () {0x2;}' unless defined(&MASTER_MTIMER_ENB);
    eval 'sub MASTER_IM_TX_TIMER_ENB () {0x4;}' unless defined(&MASTER_IM_TX_TIMER_ENB);
    eval 'sub MASTER_MANUAL_INT_ENB () {0x8;}' unless defined(&MASTER_MANUAL_INT_ENB);
    eval 'sub MASTER_IM_RX_TIMER_ENB () {0x20;}' unless defined(&MASTER_IM_RX_TIMER_ENB);
    eval 'sub MASTER_INT_RDCLR () {0x40;}' unless defined(&MASTER_INT_RDCLR);
    eval 'sub MASTER_LED_MODE () {0x200;}' unless defined(&MASTER_LED_MODE);
    eval 'sub MASTER_CHIP_REV_MASK () {0xff0000;}' unless defined(&MASTER_CHIP_REV_MASK);
    eval 'sub MASTER_CHIP_ID_MASK () {0xff000000;}' unless defined(&MASTER_CHIP_ID_MASK);
    eval 'sub MASTER_CHIP_REV_SHIFT () {16;}' unless defined(&MASTER_CHIP_REV_SHIFT);
    eval 'sub MASTER_CHIP_ID_SHIFT () {24;}' unless defined(&MASTER_CHIP_ID_SHIFT);
    eval 'sub ALE_TICK_USECS () {2;}' unless defined(&ALE_TICK_USECS);
    eval 'sub ALE_USECS {
        my($x) = @_;
	    eval q((($x) /  &ALE_TICK_USECS));
    }' unless defined(&ALE_USECS);
    eval 'sub ALE_MANUAL_TIMER () {0x1404;}' unless defined(&ALE_MANUAL_TIMER);
    eval 'sub ALE_IM_TIMER () {0x1408;}' unless defined(&ALE_IM_TIMER);
    eval 'sub IM_TIMER_TX_MASK () {0xffff;}' unless defined(&IM_TIMER_TX_MASK);
    eval 'sub IM_TIMER_RX_MASK () {0xffff0000;}' unless defined(&IM_TIMER_RX_MASK);
    eval 'sub IM_TIMER_TX_SHIFT () {0;}' unless defined(&IM_TIMER_TX_SHIFT);
    eval 'sub IM_TIMER_RX_SHIFT () {16;}' unless defined(&IM_TIMER_RX_SHIFT);
    eval 'sub ALE_IM_TIMER_MIN () {0;}' unless defined(&ALE_IM_TIMER_MIN);
    eval 'sub ALE_IM_TIMER_MAX () {130000;}' unless defined(&ALE_IM_TIMER_MAX);
    eval 'sub ALE_IM_RX_TIMER_DEFAULT () {30;}' unless defined(&ALE_IM_RX_TIMER_DEFAULT);
    eval 'sub ALE_IM_TX_TIMER_DEFAULT () {1000;}' unless defined(&ALE_IM_TX_TIMER_DEFAULT);
    eval 'sub ALE_GPHY_CTRL () {0x140c;}' unless defined(&ALE_GPHY_CTRL);
    eval 'sub GPHY_CTRL_EXT_RESET () {0x1;}' unless defined(&GPHY_CTRL_EXT_RESET);
    eval 'sub GPHY_CTRL_PIPE_MOD () {0x2;}' unless defined(&GPHY_CTRL_PIPE_MOD);
    eval 'sub GPHY_CTRL_BERT_START () {0x10;}' unless defined(&GPHY_CTRL_BERT_START);
    eval 'sub GPHY_CTRL_GALE_25M_ENB () {0x20;}' unless defined(&GPHY_CTRL_GALE_25M_ENB);
    eval 'sub GPHY_CTRL_LPW_EXIT () {0x40;}' unless defined(&GPHY_CTRL_LPW_EXIT);
    eval 'sub GPHY_CTRL_PHY_IDDQ () {0x80;}' unless defined(&GPHY_CTRL_PHY_IDDQ);
    eval 'sub GPHY_CTRL_PHY_IDDQ_DIS () {0x100;}' unless defined(&GPHY_CTRL_PHY_IDDQ_DIS);
    eval 'sub GPHY_CTRL_PCLK_SEL_DIS () {0x200;}' unless defined(&GPHY_CTRL_PCLK_SEL_DIS);
    eval 'sub GPHY_CTRL_HIB_EN () {0x400;}' unless defined(&GPHY_CTRL_HIB_EN);
    eval 'sub GPHY_CTRL_HIB_PULSE () {0x800;}' unless defined(&GPHY_CTRL_HIB_PULSE);
    eval 'sub GPHY_CTRL_SEL_ANA_RESET () {0x1000;}' unless defined(&GPHY_CTRL_SEL_ANA_RESET);
    eval 'sub GPHY_CTRL_PHY_PLL_ON () {0x2000;}' unless defined(&GPHY_CTRL_PHY_PLL_ON);
    eval 'sub GPHY_CTRL_PWDOWN_HW () {0x4000;}' unless defined(&GPHY_CTRL_PWDOWN_HW);
    eval 'sub ALE_INTR_CLR_TIMER () {0x140e;}' unless defined(&ALE_INTR_CLR_TIMER);
    eval 'sub ALE_IDLE_STATUS () {0x1410;}' unless defined(&ALE_IDLE_STATUS);
    eval 'sub IDLE_STATUS_RXMAC () {0x1;}' unless defined(&IDLE_STATUS_RXMAC);
    eval 'sub IDLE_STATUS_TXMAC () {0x2;}' unless defined(&IDLE_STATUS_TXMAC);
    eval 'sub IDLE_STATUS_RXQ () {0x4;}' unless defined(&IDLE_STATUS_RXQ);
    eval 'sub IDLE_STATUS_TXQ () {0x8;}' unless defined(&IDLE_STATUS_TXQ);
    eval 'sub IDLE_STATUS_DMARD () {0x10;}' unless defined(&IDLE_STATUS_DMARD);
    eval 'sub IDLE_STATUS_DMAWR () {0x20;}' unless defined(&IDLE_STATUS_DMAWR);
    eval 'sub IDLE_STATUS_SMB () {0x40;}' unless defined(&IDLE_STATUS_SMB);
    eval 'sub IDLE_STATUS_CMB () {0x80;}' unless defined(&IDLE_STATUS_CMB);
    eval 'sub ALE_MDIO () {0x1414;}' unless defined(&ALE_MDIO);
    eval 'sub MDIO_DATA_MASK () {0xffff;}' unless defined(&MDIO_DATA_MASK);
    eval 'sub MDIO_REG_ADDR_MASK () {0x1f0000;}' unless defined(&MDIO_REG_ADDR_MASK);
    eval 'sub MDIO_OP_READ () {0x200000;}' unless defined(&MDIO_OP_READ);
    eval 'sub MDIO_OP_WRITE () {0x;}' unless defined(&MDIO_OP_WRITE);
    eval 'sub MDIO_SUP_PREAMBLE () {0x400000;}' unless defined(&MDIO_SUP_PREAMBLE);
    eval 'sub MDIO_OP_EXECUTE () {0x800000;}' unless defined(&MDIO_OP_EXECUTE);
    eval 'sub MDIO_CLK_25_4 () {0x;}' unless defined(&MDIO_CLK_25_4);
    eval 'sub MDIO_CLK_25_6 () {0x2000000;}' unless defined(&MDIO_CLK_25_6);
    eval 'sub MDIO_CLK_25_8 () {0x3000000;}' unless defined(&MDIO_CLK_25_8);
    eval 'sub MDIO_CLK_25_10 () {0x4000000;}' unless defined(&MDIO_CLK_25_10);
    eval 'sub MDIO_CLK_25_14 () {0x5000000;}' unless defined(&MDIO_CLK_25_14);
    eval 'sub MDIO_CLK_25_20 () {0x6000000;}' unless defined(&MDIO_CLK_25_20);
    eval 'sub MDIO_CLK_25_28 () {0x7000000;}' unless defined(&MDIO_CLK_25_28);
    eval 'sub MDIO_OP_BUSY () {0x8000000;}' unless defined(&MDIO_OP_BUSY);
    eval 'sub MDIO_DATA_SHIFT () {0;}' unless defined(&MDIO_DATA_SHIFT);
    eval 'sub MDIO_REG_ADDR_SHIFT () {16;}' unless defined(&MDIO_REG_ADDR_SHIFT);
    eval 'sub MDIO_REG_ADDR {
        my($x) = @_;
	    eval q(((($x) <<  &MDIO_REG_ADDR_SHIFT) &  &MDIO_REG_ADDR_MASK));
    }' unless defined(&MDIO_REG_ADDR);
    eval 'sub ALE_PHY_ADDR () {0;}' unless defined(&ALE_PHY_ADDR);
    eval 'sub ALE_PHY_STATUS () {0x1418;}' unless defined(&ALE_PHY_STATUS);
    eval 'sub PHY_STATUS_100M () {0x20000;}' unless defined(&PHY_STATUS_100M);
    eval 'sub ALE_BIST0 () {0x141c;}' unless defined(&ALE_BIST0);
    eval 'sub BIST0_ENB () {0x1;}' unless defined(&BIST0_ENB);
    eval 'sub BIST0_SRAM_FAIL () {0x2;}' unless defined(&BIST0_SRAM_FAIL);
    eval 'sub BIST0_FUSE_FLAG () {0x4;}' unless defined(&BIST0_FUSE_FLAG);
    eval 'sub ALE_BIST1 () {0x1420;}' unless defined(&ALE_BIST1);
    eval 'sub BIST1_ENB () {0x1;}' unless defined(&BIST1_ENB);
    eval 'sub BIST1_SRAM_FAIL () {0x2;}' unless defined(&BIST1_SRAM_FAIL);
    eval 'sub BIST1_FUSE_FLAG () {0x4;}' unless defined(&BIST1_FUSE_FLAG);
    eval 'sub ALE_SERDES_LOCK () {0x1424;}' unless defined(&ALE_SERDES_LOCK);
    eval 'sub SERDES_LOCK_DET () {0x1;}' unless defined(&SERDES_LOCK_DET);
    eval 'sub SERDES_LOCK_DET_ENB () {0x2;}' unless defined(&SERDES_LOCK_DET_ENB);
    eval 'sub ALE_MAC_CFG () {0x1480;}' unless defined(&ALE_MAC_CFG);
    eval 'sub MAC_CFG_TX_ENB () {0x1;}' unless defined(&MAC_CFG_TX_ENB);
    eval 'sub MAC_CFG_RX_ENB () {0x2;}' unless defined(&MAC_CFG_RX_ENB);
    eval 'sub MAC_CFG_TX_FC () {0x4;}' unless defined(&MAC_CFG_TX_FC);
    eval 'sub MAC_CFG_RX_FC () {0x8;}' unless defined(&MAC_CFG_RX_FC);
    eval 'sub MAC_CFG_LOOP () {0x10;}' unless defined(&MAC_CFG_LOOP);
    eval 'sub MAC_CFG_FULL_DUPLEX () {0x20;}' unless defined(&MAC_CFG_FULL_DUPLEX);
    eval 'sub MAC_CFG_TX_CRC_ENB () {0x40;}' unless defined(&MAC_CFG_TX_CRC_ENB);
    eval 'sub MAC_CFG_TX_AUTO_PAD () {0x80;}' unless defined(&MAC_CFG_TX_AUTO_PAD);
    eval 'sub MAC_CFG_TX_LENCHK () {0x100;}' unless defined(&MAC_CFG_TX_LENCHK);
    eval 'sub MAC_CFG_RX_JUMBO_ENB () {0x200;}' unless defined(&MAC_CFG_RX_JUMBO_ENB);
    eval 'sub MAC_CFG_PREAMBLE_MASK () {0x3c00;}' unless defined(&MAC_CFG_PREAMBLE_MASK);
    eval 'sub MAC_CFG_VLAN_TAG_STRIP () {0x4000;}' unless defined(&MAC_CFG_VLAN_TAG_STRIP);
    eval 'sub MAC_CFG_PROMISC () {0x8000;}' unless defined(&MAC_CFG_PROMISC);
    eval 'sub MAC_CFG_TX_PAUSE () {0x10000;}' unless defined(&MAC_CFG_TX_PAUSE);
    eval 'sub MAC_CFG_SCNT () {0x20000;}' unless defined(&MAC_CFG_SCNT);
    eval 'sub MAC_CFG_SYNC_RST_TX () {0x40000;}' unless defined(&MAC_CFG_SYNC_RST_TX);
    eval 'sub MAC_CFG_SPEED_MASK () {0x300000;}' unless defined(&MAC_CFG_SPEED_MASK);
    eval 'sub MAC_CFG_SPEED_10_100 () {0x100000;}' unless defined(&MAC_CFG_SPEED_10_100);
    eval 'sub MAC_CFG_SPEED_1000 () {0x200000;}' unless defined(&MAC_CFG_SPEED_1000);
    eval 'sub MAC_CFG_DBG_TX_BACKOFF () {0x400000;}' unless defined(&MAC_CFG_DBG_TX_BACKOFF);
    eval 'sub MAC_CFG_TX_JUMBO_ENB () {0x800000;}' unless defined(&MAC_CFG_TX_JUMBO_ENB);
    eval 'sub MAC_CFG_RXCSUM_ENB () {0x1000000;}' unless defined(&MAC_CFG_RXCSUM_ENB);
    eval 'sub MAC_CFG_ALLMULTI () {0x2000000;}' unless defined(&MAC_CFG_ALLMULTI);
    eval 'sub MAC_CFG_BCAST () {0x4000000;}' unless defined(&MAC_CFG_BCAST);
    eval 'sub MAC_CFG_DBG () {0x8000000;}' unless defined(&MAC_CFG_DBG);
    eval 'sub MAC_CFG_PREAMBLE_SHIFT () {10;}' unless defined(&MAC_CFG_PREAMBLE_SHIFT);
    eval 'sub MAC_CFG_PREAMBLE_DEFAULT () {7;}' unless defined(&MAC_CFG_PREAMBLE_DEFAULT);
    eval 'sub ALE_IPG_IFG_CFG () {0x1484;}' unless defined(&ALE_IPG_IFG_CFG);
    eval 'sub IPG_IFG_IPGT_MASK () {0x7f;}' unless defined(&IPG_IFG_IPGT_MASK);
    eval 'sub IPG_IFG_MIFG_MASK () {0xff00;}' unless defined(&IPG_IFG_MIFG_MASK);
    eval 'sub IPG_IFG_IPG1_MASK () {0x7f0000;}' unless defined(&IPG_IFG_IPG1_MASK);
    eval 'sub IPG_IFG_IPG2_MASK () {0x7f000000;}' unless defined(&IPG_IFG_IPG2_MASK);
    eval 'sub IPG_IFG_IPGT_SHIFT () {0;}' unless defined(&IPG_IFG_IPGT_SHIFT);
    eval 'sub IPG_IFG_IPGT_DEFAULT () {0x60;}' unless defined(&IPG_IFG_IPGT_DEFAULT);
    eval 'sub IPG_IFG_MIFG_SHIFT () {8;}' unless defined(&IPG_IFG_MIFG_SHIFT);
    eval 'sub IPG_IFG_MIFG_DEFAULT () {0x50;}' unless defined(&IPG_IFG_MIFG_DEFAULT);
    eval 'sub IPG_IFG_IPG1_SHIFT () {16;}' unless defined(&IPG_IFG_IPG1_SHIFT);
    eval 'sub IPG_IFG_IPG1_DEFAULT () {0x40;}' unless defined(&IPG_IFG_IPG1_DEFAULT);
    eval 'sub IPG_IFG_IPG2_SHIFT () {24;}' unless defined(&IPG_IFG_IPG2_SHIFT);
    eval 'sub IPG_IFG_IPG2_DEFAULT () {0x60;}' unless defined(&IPG_IFG_IPG2_DEFAULT);
    eval 'sub ALE_PAR0 () {0x1488;}' unless defined(&ALE_PAR0);
    eval 'sub ALE_PAR1 () {0x148c;}' unless defined(&ALE_PAR1);
    eval 'sub ALE_MAR0 () {0x1490;}' unless defined(&ALE_MAR0);
    eval 'sub ALE_MAR1 () {0x1494;}' unless defined(&ALE_MAR1);
    eval 'sub ALE_HDPX_CFG () {0x1498;}' unless defined(&ALE_HDPX_CFG);
    eval 'sub HDPX_CFG_LCOL_MASK () {0x3ff;}' unless defined(&HDPX_CFG_LCOL_MASK);
    eval 'sub HDPX_CFG_RETRY_MASK () {0xf000;}' unless defined(&HDPX_CFG_RETRY_MASK);
    eval 'sub HDPX_CFG_EXC_DEF_EN () {0x10000;}' unless defined(&HDPX_CFG_EXC_DEF_EN);
    eval 'sub HDPX_CFG_NO_BACK_C () {0x20000;}' unless defined(&HDPX_CFG_NO_BACK_C);
    eval 'sub HDPX_CFG_NO_BACK_P () {0x40000;}' unless defined(&HDPX_CFG_NO_BACK_P);
    eval 'sub HDPX_CFG_ABEBE () {0x80000;}' unless defined(&HDPX_CFG_ABEBE);
    eval 'sub HDPX_CFG_ABEBT_MASK () {0xf00000;}' unless defined(&HDPX_CFG_ABEBT_MASK);
    eval 'sub HDPX_CFG_JAMIPG_MASK () {0xf000000;}' unless defined(&HDPX_CFG_JAMIPG_MASK);
    eval 'sub HDPX_CFG_LCOL_SHIFT () {0;}' unless defined(&HDPX_CFG_LCOL_SHIFT);
    eval 'sub HDPX_CFG_LCOL_DEFAULT () {0x37;}' unless defined(&HDPX_CFG_LCOL_DEFAULT);
    eval 'sub HDPX_CFG_RETRY_SHIFT () {12;}' unless defined(&HDPX_CFG_RETRY_SHIFT);
    eval 'sub HDPX_CFG_RETRY_DEFAULT () {0xf;}' unless defined(&HDPX_CFG_RETRY_DEFAULT);
    eval 'sub HDPX_CFG_ABEBT_SHIFT () {20;}' unless defined(&HDPX_CFG_ABEBT_SHIFT);
    eval 'sub HDPX_CFG_ABEBT_DEFAULT () {0xa;}' unless defined(&HDPX_CFG_ABEBT_DEFAULT);
    eval 'sub HDPX_CFG_JAMIPG_SHIFT () {24;}' unless defined(&HDPX_CFG_JAMIPG_SHIFT);
    eval 'sub HDPX_CFG_JAMIPG_DEFAULT () {0x7;}' unless defined(&HDPX_CFG_JAMIPG_DEFAULT);
    eval 'sub ALE_FRAME_SIZE () {0x149c;}' unless defined(&ALE_FRAME_SIZE);
    eval 'sub ALE_WOL_CFG () {0x14a0;}' unless defined(&ALE_WOL_CFG);
    eval 'sub WOL_CFG_PATTERN () {0x1;}' unless defined(&WOL_CFG_PATTERN);
    eval 'sub WOL_CFG_PATTERN_ENB () {0x2;}' unless defined(&WOL_CFG_PATTERN_ENB);
    eval 'sub WOL_CFG_MAGIC () {0x4;}' unless defined(&WOL_CFG_MAGIC);
    eval 'sub WOL_CFG_MAGIC_ENB () {0x8;}' unless defined(&WOL_CFG_MAGIC_ENB);
    eval 'sub WOL_CFG_LINK_CHG () {0x10;}' unless defined(&WOL_CFG_LINK_CHG);
    eval 'sub WOL_CFG_LINK_CHG_ENB () {0x20;}' unless defined(&WOL_CFG_LINK_CHG_ENB);
    eval 'sub WOL_CFG_PATTERN_DET () {0x100;}' unless defined(&WOL_CFG_PATTERN_DET);
    eval 'sub WOL_CFG_MAGIC_DET () {0x200;}' unless defined(&WOL_CFG_MAGIC_DET);
    eval 'sub WOL_CFG_LINK_CHG_DET () {0x400;}' unless defined(&WOL_CFG_LINK_CHG_DET);
    eval 'sub WOL_CFG_CLK_SWITCH_ENB () {0x8000;}' unless defined(&WOL_CFG_CLK_SWITCH_ENB);
    eval 'sub WOL_CFG_PATTERN0 () {0x10000;}' unless defined(&WOL_CFG_PATTERN0);
    eval 'sub WOL_CFG_PATTERN1 () {0x20000;}' unless defined(&WOL_CFG_PATTERN1);
    eval 'sub WOL_CFG_PATTERN2 () {0x40000;}' unless defined(&WOL_CFG_PATTERN2);
    eval 'sub WOL_CFG_PATTERN3 () {0x80000;}' unless defined(&WOL_CFG_PATTERN3);
    eval 'sub WOL_CFG_PATTERN4 () {0x100000;}' unless defined(&WOL_CFG_PATTERN4);
    eval 'sub WOL_CFG_PATTERN5 () {0x200000;}' unless defined(&WOL_CFG_PATTERN5);
    eval 'sub WOL_CFG_PATTERN6 () {0x400000;}' unless defined(&WOL_CFG_PATTERN6);
    eval 'sub ALE_PATTERN_CFG0 () {0x14a4;}' unless defined(&ALE_PATTERN_CFG0);
    eval 'sub PATTERN_CFG_0_LEN_MASK () {0x7f;}' unless defined(&PATTERN_CFG_0_LEN_MASK);
    eval 'sub PATTERN_CFG_1_LEN_MASK () {0x7f00;}' unless defined(&PATTERN_CFG_1_LEN_MASK);
    eval 'sub PATTERN_CFG_2_LEN_MASK () {0x7f0000;}' unless defined(&PATTERN_CFG_2_LEN_MASK);
    eval 'sub PATTERN_CFG_3_LEN_MASK () {0x7f000000;}' unless defined(&PATTERN_CFG_3_LEN_MASK);
    eval 'sub ALE_PATTERN_CFG1 () {0x14a8;}' unless defined(&ALE_PATTERN_CFG1);
    eval 'sub PATTERN_CFG_4_LEN_MASK () {0x7f;}' unless defined(&PATTERN_CFG_4_LEN_MASK);
    eval 'sub PATTERN_CFG_5_LEN_MASK () {0x7f00;}' unless defined(&PATTERN_CFG_5_LEN_MASK);
    eval 'sub PATTERN_CFG_6_LEN_MASK () {0x7f0000;}' unless defined(&PATTERN_CFG_6_LEN_MASK);
    eval 'sub ALE_RSS_KEY0 () {0x14b0;}' unless defined(&ALE_RSS_KEY0);
    eval 'sub ALE_RSS_KEY1 () {0x14b4;}' unless defined(&ALE_RSS_KEY1);
    eval 'sub ALE_RSS_KEY2 () {0x14b8;}' unless defined(&ALE_RSS_KEY2);
    eval 'sub ALE_RSS_KEY3 () {0x14bc;}' unless defined(&ALE_RSS_KEY3);
    eval 'sub ALE_RSS_KEY4 () {0x14c0;}' unless defined(&ALE_RSS_KEY4);
    eval 'sub ALE_RSS_KEY5 () {0x14c4;}' unless defined(&ALE_RSS_KEY5);
    eval 'sub ALE_RSS_KEY6 () {0x14c8;}' unless defined(&ALE_RSS_KEY6);
    eval 'sub ALE_RSS_KEY7 () {0x14cc;}' unless defined(&ALE_RSS_KEY7);
    eval 'sub ALE_RSS_KEY8 () {0x14d0;}' unless defined(&ALE_RSS_KEY8);
    eval 'sub ALE_RSS_KEY9 () {0x14d4;}' unless defined(&ALE_RSS_KEY9);
    eval 'sub ALE_RSS_IDT_TABLE4 () {0x14e0;}' unless defined(&ALE_RSS_IDT_TABLE4);
    eval 'sub ALE_RSS_IDT_TABLE5 () {0x14e4;}' unless defined(&ALE_RSS_IDT_TABLE5);
    eval 'sub ALE_RSS_IDT_TABLE6 () {0x14e8;}' unless defined(&ALE_RSS_IDT_TABLE6);
    eval 'sub ALE_RSS_IDT_TABLE7 () {0x14ec;}' unless defined(&ALE_RSS_IDT_TABLE7);
    eval 'sub ALE_SRAM_RD_ADDR () {0x1500;}' unless defined(&ALE_SRAM_RD_ADDR);
    eval 'sub ALE_SRAM_RD_LEN () {0x1504;}' unless defined(&ALE_SRAM_RD_LEN);
    eval 'sub ALE_SRAM_RRD_ADDR () {0x1508;}' unless defined(&ALE_SRAM_RRD_ADDR);
    eval 'sub ALE_SRAM_RRD_LEN () {0x150c;}' unless defined(&ALE_SRAM_RRD_LEN);
    eval 'sub ALE_SRAM_TPD_ADDR () {0x1510;}' unless defined(&ALE_SRAM_TPD_ADDR);
    eval 'sub ALE_SRAM_TPD_LEN () {0x1514;}' unless defined(&ALE_SRAM_TPD_LEN);
    eval 'sub ALE_SRAM_TRD_ADDR () {0x1518;}' unless defined(&ALE_SRAM_TRD_ADDR);
    eval 'sub ALE_SRAM_TRD_LEN () {0x151c;}' unless defined(&ALE_SRAM_TRD_LEN);
    eval 'sub ALE_SRAM_RX_FIFO_ADDR () {0x1520;}' unless defined(&ALE_SRAM_RX_FIFO_ADDR);
    eval 'sub ALE_SRAM_RX_FIFO_LEN () {0x1524;}' unless defined(&ALE_SRAM_RX_FIFO_LEN);
    eval 'sub ALE_SRAM_TX_FIFO_ADDR () {0x1528;}' unless defined(&ALE_SRAM_TX_FIFO_ADDR);
    eval 'sub ALE_SRAM_TX_FIFO_LEN () {0x152c;}' unless defined(&ALE_SRAM_TX_FIFO_LEN);
    eval 'sub ALE_SRAM_TCPH_ADDR () {0x1530;}' unless defined(&ALE_SRAM_TCPH_ADDR);
    eval 'sub SRAM_TCPH_ADDR_MASK () {0xfff;}' unless defined(&SRAM_TCPH_ADDR_MASK);
    eval 'sub SRAM_PATH_ADDR_MASK () {0xfff0000;}' unless defined(&SRAM_PATH_ADDR_MASK);
    eval 'sub SRAM_TCPH_ADDR_SHIFT () {0;}' unless defined(&SRAM_TCPH_ADDR_SHIFT);
    eval 'sub SRAM_PATH_ADDR_SHIFT () {16;}' unless defined(&SRAM_PATH_ADDR_SHIFT);
    eval 'sub ALE_DMA_BLOCK () {0x1534;}' unless defined(&ALE_DMA_BLOCK);
    eval 'sub DMA_BLOCK_LOAD () {0x1;}' unless defined(&DMA_BLOCK_LOAD);
    eval 'sub ALE_RXF3_ADDR_HI () {0x153c;}' unless defined(&ALE_RXF3_ADDR_HI);
    eval 'sub ALE_TPD_ADDR_HI () {0x1540;}' unless defined(&ALE_TPD_ADDR_HI);
    eval 'sub ALE_RXF0_PAGE0_ADDR_LO () {0x1544;}' unless defined(&ALE_RXF0_PAGE0_ADDR_LO);
    eval 'sub ALE_RXF0_PAGE1_ADDR_LO () {0x1548;}' unless defined(&ALE_RXF0_PAGE1_ADDR_LO);
    eval 'sub ALE_TPD_ADDR_LO () {0x154c;}' unless defined(&ALE_TPD_ADDR_LO);
    eval 'sub ALE_RXF1_ADDR_HI () {0x1550;}' unless defined(&ALE_RXF1_ADDR_HI);
    eval 'sub ALE_RXF2_ADDR_HI () {0x1554;}' unless defined(&ALE_RXF2_ADDR_HI);
    eval 'sub ALE_RXF_PAGE_SIZE () {0x1558;}' unless defined(&ALE_RXF_PAGE_SIZE);
    eval 'sub ALE_TPD_CNT () {0x155c;}' unless defined(&ALE_TPD_CNT);
    eval 'sub TPD_CNT_MASK () {0x3ff;}' unless defined(&TPD_CNT_MASK);
    eval 'sub TPD_CNT_SHIFT () {0;}' unless defined(&TPD_CNT_SHIFT);
    eval 'sub ALE_RSS_IDT_TABLE0 () {0x1560;}' unless defined(&ALE_RSS_IDT_TABLE0);
    eval 'sub ALE_RSS_IDT_TABLE1 () {0x1564;}' unless defined(&ALE_RSS_IDT_TABLE1);
    eval 'sub ALE_RSS_IDT_TABLE2 () {0x1568;}' unless defined(&ALE_RSS_IDT_TABLE2);
    eval 'sub ALE_RSS_IDT_TABLE3 () {0x156c;}' unless defined(&ALE_RSS_IDT_TABLE3);
    eval 'sub ALE_RSS_HASH_VALUE () {0x1570;}' unless defined(&ALE_RSS_HASH_VALUE);
    eval 'sub ALE_RSS_HASH_FLAG () {0x1574;}' unless defined(&ALE_RSS_HASH_FLAG);
    eval 'sub ALE_RSS_CPU () {0x157c;}' unless defined(&ALE_RSS_CPU);
    eval 'sub ALE_TXQ_CFG () {0x1580;}' unless defined(&ALE_TXQ_CFG);
    eval 'sub TXQ_CFG_TPD_BURST_MASK () {0xf;}' unless defined(&TXQ_CFG_TPD_BURST_MASK);
    eval 'sub TXQ_CFG_ENB () {0x20;}' unless defined(&TXQ_CFG_ENB);
    eval 'sub TXQ_CFG_ENHANCED_MODE () {0x40;}' unless defined(&TXQ_CFG_ENHANCED_MODE);
    eval 'sub TXQ_CFG_TX_FIFO_BURST_MASK () {0xffff0000;}' unless defined(&TXQ_CFG_TX_FIFO_BURST_MASK);
    eval 'sub TXQ_CFG_TPD_BURST_SHIFT () {0;}' unless defined(&TXQ_CFG_TPD_BURST_SHIFT);
    eval 'sub TXQ_CFG_TPD_BURST_DEFAULT () {4;}' unless defined(&TXQ_CFG_TPD_BURST_DEFAULT);
    eval 'sub TXQ_CFG_TX_FIFO_BURST_SHIFT () {16;}' unless defined(&TXQ_CFG_TX_FIFO_BURST_SHIFT);
    eval 'sub TXQ_CFG_TX_FIFO_BURST_DEFAULT () {256;}' unless defined(&TXQ_CFG_TX_FIFO_BURST_DEFAULT);
    eval 'sub ALE_TX_JUMBO_THRESH () {0x1584;}' unless defined(&ALE_TX_JUMBO_THRESH);
    eval 'sub TX_JUMBO_THRESH_MASK () {0x7ff;}' unless defined(&TX_JUMBO_THRESH_MASK);
    eval 'sub TX_JUMBO_THRESH_SHIFT () {0;}' unless defined(&TX_JUMBO_THRESH_SHIFT);
    eval 'sub TX_JUMBO_THRESH_UNIT () {8;}' unless defined(&TX_JUMBO_THRESH_UNIT);
    eval 'sub TX_JUMBO_THRESH_UNIT_SHIFT () {3;}' unless defined(&TX_JUMBO_THRESH_UNIT_SHIFT);
    eval 'sub ALE_RXQ_CFG () {0x15a0;}' unless defined(&ALE_RXQ_CFG);
    eval 'sub RXQ_CFG_ALIGN_32 () {0x;}' unless defined(&RXQ_CFG_ALIGN_32);
    eval 'sub RXQ_CFG_ALIGN_64 () {0x1;}' unless defined(&RXQ_CFG_ALIGN_64);
    eval 'sub RXQ_CFG_ALIGN_128 () {0x2;}' unless defined(&RXQ_CFG_ALIGN_128);
    eval 'sub RXQ_CFG_ALIGN_256 () {0x3;}' unless defined(&RXQ_CFG_ALIGN_256);
    eval 'sub RXQ_CFG_QUEUE1_ENB () {0x10;}' unless defined(&RXQ_CFG_QUEUE1_ENB);
    eval 'sub RXQ_CFG_QUEUE2_ENB () {0x20;}' unless defined(&RXQ_CFG_QUEUE2_ENB);
    eval 'sub RXQ_CFG_QUEUE3_ENB () {0x40;}' unless defined(&RXQ_CFG_QUEUE3_ENB);
    eval 'sub RXQ_CFG_IPV6_CSUM_VERIFY () {0x80;}' unless defined(&RXQ_CFG_IPV6_CSUM_VERIFY);
    eval 'sub RXQ_CFG_RSS_HASH_TBL_LEN_MASK () {0xff00;}' unless defined(&RXQ_CFG_RSS_HASH_TBL_LEN_MASK);
    eval 'sub RXQ_CFG_RSS_HASH_IPV4 () {0x10000;}' unless defined(&RXQ_CFG_RSS_HASH_IPV4);
    eval 'sub RXQ_CFG_RSS_HASH_IPV4_TCP () {0x20000;}' unless defined(&RXQ_CFG_RSS_HASH_IPV4_TCP);
    eval 'sub RXQ_CFG_RSS_HASH_IPV6 () {0x40000;}' unless defined(&RXQ_CFG_RSS_HASH_IPV6);
    eval 'sub RXQ_CFG_RSS_HASH_IPV6_TCP () {0x80000;}' unless defined(&RXQ_CFG_RSS_HASH_IPV6_TCP);
    eval 'sub RXQ_CFG_RSS_MODE_DIS () {0x;}' unless defined(&RXQ_CFG_RSS_MODE_DIS);
    eval 'sub RXQ_CFG_RSS_MODE_SQSINT () {0x4000000;}' unless defined(&RXQ_CFG_RSS_MODE_SQSINT);
    eval 'sub RXQ_CFG_RSS_MODE_MQUESINT () {0x8000000;}' unless defined(&RXQ_CFG_RSS_MODE_MQUESINT);
    eval 'sub RXQ_CFG_RSS_MODE_MQUEMINT () {0xc000000;}' unless defined(&RXQ_CFG_RSS_MODE_MQUEMINT);
    eval 'sub RXQ_CFG_NIP_QUEUE_SEL_TBL () {0x10000000;}' unless defined(&RXQ_CFG_NIP_QUEUE_SEL_TBL);
    eval 'sub RXQ_CFG_RSS_HASH_ENB () {0x20000000;}' unless defined(&RXQ_CFG_RSS_HASH_ENB);
    eval 'sub RXQ_CFG_CUT_THROUGH_ENB () {0x40000000;}' unless defined(&RXQ_CFG_CUT_THROUGH_ENB);
    eval 'sub RXQ_CFG_ENB () {0x80000000;}' unless defined(&RXQ_CFG_ENB);
    eval 'sub RXQ_CFG_RSS_HASH_TBL_LEN_SHIFT () {8;}' unless defined(&RXQ_CFG_RSS_HASH_TBL_LEN_SHIFT);
    eval 'sub ALE_RX_JUMBO_THRESH () {0x15a4;}' unless defined(&ALE_RX_JUMBO_THRESH);
    eval 'sub RX_JUMBO_THRESH_MASK () {0x7ff;}' unless defined(&RX_JUMBO_THRESH_MASK);
    eval 'sub RX_JUMBO_LKAH_MASK () {0x7800;}' unless defined(&RX_JUMBO_LKAH_MASK);
    eval 'sub RX_JUMBO_THRESH_MASK_SHIFT () {0;}' unless defined(&RX_JUMBO_THRESH_MASK_SHIFT);
    eval 'sub RX_JUMBO_THRESH_UNIT () {8;}' unless defined(&RX_JUMBO_THRESH_UNIT);
    eval 'sub RX_JUMBO_THRESH_UNIT_SHIFT () {3;}' unless defined(&RX_JUMBO_THRESH_UNIT_SHIFT);
    eval 'sub RX_JUMBO_LKAH_SHIFT () {11;}' unless defined(&RX_JUMBO_LKAH_SHIFT);
    eval 'sub RX_JUMBO_LKAH_DEFAULT () {1;}' unless defined(&RX_JUMBO_LKAH_DEFAULT);
    eval 'sub ALE_RX_FIFO_PAUSE_THRESH () {0x15a8;}' unless defined(&ALE_RX_FIFO_PAUSE_THRESH);
    eval 'sub RX_FIFO_PAUSE_THRESH_LO_MASK () {0xfff;}' unless defined(&RX_FIFO_PAUSE_THRESH_LO_MASK);
    eval 'sub RX_FIFO_PAUSE_THRESH_HI_MASK () {0xfff0000;}' unless defined(&RX_FIFO_PAUSE_THRESH_HI_MASK);
    eval 'sub RX_FIFO_PAUSE_THRESH_LO_SHIFT () {0;}' unless defined(&RX_FIFO_PAUSE_THRESH_LO_SHIFT);
    eval 'sub RX_FIFO_PAUSE_THRESH_HI_SHIFT () {16;}' unless defined(&RX_FIFO_PAUSE_THRESH_HI_SHIFT);
    eval 'sub ALE_CMB_RXF1 () {0x15b4;}' unless defined(&ALE_CMB_RXF1);
    eval 'sub ALE_CMB_RXF2 () {0x15b8;}' unless defined(&ALE_CMB_RXF2);
    eval 'sub ALE_CMB_RXF3 () {0x15bc;}' unless defined(&ALE_CMB_RXF3);
    eval 'sub ALE_DMA_CFG () {0x15c0;}' unless defined(&ALE_DMA_CFG);
    eval 'sub DMA_CFG_IN_ORDER () {0x1;}' unless defined(&DMA_CFG_IN_ORDER);
    eval 'sub DMA_CFG_ENH_ORDER () {0x2;}' unless defined(&DMA_CFG_ENH_ORDER);
    eval 'sub DMA_CFG_OUT_ORDER () {0x4;}' unless defined(&DMA_CFG_OUT_ORDER);
    eval 'sub DMA_CFG_RCB_64 () {0x;}' unless defined(&DMA_CFG_RCB_64);
    eval 'sub DMA_CFG_RCB_128 () {0x8;}' unless defined(&DMA_CFG_RCB_128);
    eval 'sub DMA_CFG_RD_BURST_128 () {0x;}' unless defined(&DMA_CFG_RD_BURST_128);
    eval 'sub DMA_CFG_RD_BURST_256 () {0x10;}' unless defined(&DMA_CFG_RD_BURST_256);
    eval 'sub DMA_CFG_RD_BURST_512 () {0x20;}' unless defined(&DMA_CFG_RD_BURST_512);
    eval 'sub DMA_CFG_RD_BURST_1024 () {0x30;}' unless defined(&DMA_CFG_RD_BURST_1024);
    eval 'sub DMA_CFG_RD_BURST_2048 () {0x40;}' unless defined(&DMA_CFG_RD_BURST_2048);
    eval 'sub DMA_CFG_RD_BURST_4096 () {0x50;}' unless defined(&DMA_CFG_RD_BURST_4096);
    eval 'sub DMA_CFG_WR_BURST_128 () {0x;}' unless defined(&DMA_CFG_WR_BURST_128);
    eval 'sub DMA_CFG_WR_BURST_256 () {0x80;}' unless defined(&DMA_CFG_WR_BURST_256);
    eval 'sub DMA_CFG_WR_BURST_512 () {0x100;}' unless defined(&DMA_CFG_WR_BURST_512);
    eval 'sub DMA_CFG_WR_BURST_1024 () {0x180;}' unless defined(&DMA_CFG_WR_BURST_1024);
    eval 'sub DMA_CFG_WR_BURST_2048 () {0x200;}' unless defined(&DMA_CFG_WR_BURST_2048);
    eval 'sub DMA_CFG_WR_BURST_4096 () {0x280;}' unless defined(&DMA_CFG_WR_BURST_4096);
    eval 'sub DMA_CFG_RD_REQ_PRI () {0x400;}' unless defined(&DMA_CFG_RD_REQ_PRI);
    eval 'sub DMA_CFG_RD_DELAY_CNT_MASK () {0xf800;}' unless defined(&DMA_CFG_RD_DELAY_CNT_MASK);
    eval 'sub DMA_CFG_WR_DELAY_CNT_MASK () {0xf0000;}' unless defined(&DMA_CFG_WR_DELAY_CNT_MASK);
    eval 'sub DMA_CFG_TXCMB_ENB () {0x100000;}' unless defined(&DMA_CFG_TXCMB_ENB);
    eval 'sub DMA_CFG_RXCMB_ENB () {0x200000;}' unless defined(&DMA_CFG_RXCMB_ENB);
    eval 'sub DMA_CFG_RD_BURST_MASK () {0x7;}' unless defined(&DMA_CFG_RD_BURST_MASK);
    eval 'sub DMA_CFG_RD_BURST_SHIFT () {4;}' unless defined(&DMA_CFG_RD_BURST_SHIFT);
    eval 'sub DMA_CFG_WR_BURST_MASK () {0x7;}' unless defined(&DMA_CFG_WR_BURST_MASK);
    eval 'sub DMA_CFG_WR_BURST_SHIFT () {7;}' unless defined(&DMA_CFG_WR_BURST_SHIFT);
    eval 'sub DMA_CFG_RD_DELAY_CNT_SHIFT () {11;}' unless defined(&DMA_CFG_RD_DELAY_CNT_SHIFT);
    eval 'sub DMA_CFG_WR_DELAY_CNT_SHIFT () {16;}' unless defined(&DMA_CFG_WR_DELAY_CNT_SHIFT);
    eval 'sub DMA_CFG_RD_DELAY_CNT_DEFAULT () {15;}' unless defined(&DMA_CFG_RD_DELAY_CNT_DEFAULT);
    eval 'sub DMA_CFG_WR_DELAY_CNT_DEFAULT () {4;}' unless defined(&DMA_CFG_WR_DELAY_CNT_DEFAULT);
    eval 'sub ALE_SMB_STAT_TIMER () {0x15c4;}' unless defined(&ALE_SMB_STAT_TIMER);
    eval 'sub ALE_INT_TRIG_THRESH () {0x15c8;}' unless defined(&ALE_INT_TRIG_THRESH);
    eval 'sub INT_TRIG_TX_THRESH_MASK () {0xffff;}' unless defined(&INT_TRIG_TX_THRESH_MASK);
    eval 'sub INT_TRIG_RX_THRESH_MASK () {0xffff0000;}' unless defined(&INT_TRIG_RX_THRESH_MASK);
    eval 'sub INT_TRIG_TX_THRESH_SHIFT () {0;}' unless defined(&INT_TRIG_TX_THRESH_SHIFT);
    eval 'sub INT_TRIG_RX_THRESH_SHIFT () {16;}' unless defined(&INT_TRIG_RX_THRESH_SHIFT);
    eval 'sub ALE_INT_TRIG_TIMER () {0x15cc;}' unless defined(&ALE_INT_TRIG_TIMER);
    eval 'sub INT_TRIG_TX_TIMER_MASK () {0xffff;}' unless defined(&INT_TRIG_TX_TIMER_MASK);
    eval 'sub INT_TRIG_RX_TIMER_MASK () {0xffff;}' unless defined(&INT_TRIG_RX_TIMER_MASK);
    eval 'sub INT_TRIG_TX_TIMER_SHIFT () {0;}' unless defined(&INT_TRIG_TX_TIMER_SHIFT);
    eval 'sub INT_TRIG_RX_TIMER_SHIFT () {16;}' unless defined(&INT_TRIG_RX_TIMER_SHIFT);
    eval 'sub ALE_RXF1_PAGE0_ADDR_LO () {0x15d0;}' unless defined(&ALE_RXF1_PAGE0_ADDR_LO);
    eval 'sub ALE_RXF1_PAGE1_ADDR_LO () {0x15d4;}' unless defined(&ALE_RXF1_PAGE1_ADDR_LO);
    eval 'sub ALE_RXF2_PAGE0_ADDR_LO () {0x15d8;}' unless defined(&ALE_RXF2_PAGE0_ADDR_LO);
    eval 'sub ALE_RXF2_PAGE1_ADDR_LO () {0x15dc;}' unless defined(&ALE_RXF2_PAGE1_ADDR_LO);
    eval 'sub ALE_RXF3_PAGE0_ADDR_LO () {0x15e0;}' unless defined(&ALE_RXF3_PAGE0_ADDR_LO);
    eval 'sub ALE_RXF3_PAGE1_ADDR_LO () {0x15e4;}' unless defined(&ALE_RXF3_PAGE1_ADDR_LO);
    eval 'sub ALE_MBOX_TPD_PROD_IDX () {0x15f0;}' unless defined(&ALE_MBOX_TPD_PROD_IDX);
    eval 'sub ALE_RXF0_PAGE0 () {0x15f4;}' unless defined(&ALE_RXF0_PAGE0);
    eval 'sub ALE_RXF0_PAGE1 () {0x15f5;}' unless defined(&ALE_RXF0_PAGE1);
    eval 'sub ALE_RXF1_PAGE0 () {0x15f6;}' unless defined(&ALE_RXF1_PAGE0);
    eval 'sub ALE_RXF1_PAGE1 () {0x15f7;}' unless defined(&ALE_RXF1_PAGE1);
    eval 'sub ALE_RXF2_PAGE0 () {0x15f8;}' unless defined(&ALE_RXF2_PAGE0);
    eval 'sub ALE_RXF2_PAGE1 () {0x15f9;}' unless defined(&ALE_RXF2_PAGE1);
    eval 'sub ALE_RXF3_PAGE0 () {0x15fa;}' unless defined(&ALE_RXF3_PAGE0);
    eval 'sub ALE_RXF3_PAGE1 () {0x15fb;}' unless defined(&ALE_RXF3_PAGE1);
    eval 'sub RXF_VALID () {0x1;}' unless defined(&RXF_VALID);
    eval 'sub ALE_INTR_STATUS () {0x1600;}' unless defined(&ALE_INTR_STATUS);
    eval 'sub INTR_SMB () {0x1;}' unless defined(&INTR_SMB);
    eval 'sub INTR_TIMER () {0x2;}' unless defined(&INTR_TIMER);
    eval 'sub INTR_MANUAL_TIMER () {0x4;}' unless defined(&INTR_MANUAL_TIMER);
    eval 'sub INTR_RX_FIFO_OFLOW () {0x8;}' unless defined(&INTR_RX_FIFO_OFLOW);
    eval 'sub INTR_RXF0_OFLOW () {0x10;}' unless defined(&INTR_RXF0_OFLOW);
    eval 'sub INTR_RXF1_OFLOW () {0x20;}' unless defined(&INTR_RXF1_OFLOW);
    eval 'sub INTR_RXF2_OFLOW () {0x40;}' unless defined(&INTR_RXF2_OFLOW);
    eval 'sub INTR_RXF3_OFLOW () {0x80;}' unless defined(&INTR_RXF3_OFLOW);
    eval 'sub INTR_TX_FIFO_UNDERRUN () {0x100;}' unless defined(&INTR_TX_FIFO_UNDERRUN);
    eval 'sub INTR_RX0_PAGE_FULL () {0x200;}' unless defined(&INTR_RX0_PAGE_FULL);
    eval 'sub INTR_DMA_RD_TO_RST () {0x400;}' unless defined(&INTR_DMA_RD_TO_RST);
    eval 'sub INTR_DMA_WR_TO_RST () {0x800;}' unless defined(&INTR_DMA_WR_TO_RST);
    eval 'sub INTR_GPHY () {0x1000;}' unless defined(&INTR_GPHY);
    eval 'sub INTR_TX_CREDIT () {0x2000;}' unless defined(&INTR_TX_CREDIT);
    eval 'sub INTR_GPHY_LOW_PW () {0x4000;}' unless defined(&INTR_GPHY_LOW_PW);
    eval 'sub INTR_RX_PKT () {0x10000;}' unless defined(&INTR_RX_PKT);
    eval 'sub INTR_TX_PKT () {0x20000;}' unless defined(&INTR_TX_PKT);
    eval 'sub INTR_TX_DMA () {0x40000;}' unless defined(&INTR_TX_DMA);
    eval 'sub INTR_RX_PKT1 () {0x80000;}' unless defined(&INTR_RX_PKT1);
    eval 'sub INTR_RX_PKT2 () {0x100000;}' unless defined(&INTR_RX_PKT2);
    eval 'sub INTR_RX_PKT3 () {0x200000;}' unless defined(&INTR_RX_PKT3);
    eval 'sub INTR_MAC_RX () {0x400000;}' unless defined(&INTR_MAC_RX);
    eval 'sub INTR_MAC_TX () {0x800000;}' unless defined(&INTR_MAC_TX);
    eval 'sub INTR_UNDERRUN () {0x1000000;}' unless defined(&INTR_UNDERRUN);
    eval 'sub INTR_FRAME_ERROR () {0x2000000;}' unless defined(&INTR_FRAME_ERROR);
    eval 'sub INTR_FRAME_OK () {0x4000000;}' unless defined(&INTR_FRAME_OK);
    eval 'sub INTR_CSUM_ERROR () {0x8000000;}' unless defined(&INTR_CSUM_ERROR);
    eval 'sub INTR_PHY_LINK_DOWN () {0x10000000;}' unless defined(&INTR_PHY_LINK_DOWN);
    eval 'sub INTR_DIS_INT () {0x80000000;}' unless defined(&INTR_DIS_INT);
    eval 'sub ALE_INTR_MASK () {0x1604;}' unless defined(&ALE_INTR_MASK);
    eval 'sub ALE_INTRS () {( &INTR_DMA_RD_TO_RST |  &INTR_DMA_WR_TO_RST |  &INTR_RX_PKT |  &INTR_TX_PKT |  &INTR_RX_FIFO_OFLOW |  &INTR_TX_FIFO_UNDERRUN);}' unless defined(&ALE_INTRS);
    eval 'sub ALE_RX_MIB_BASE () {0x1700;}' unless defined(&ALE_RX_MIB_BASE);
    eval 'sub ALE_TX_MIB_BASE () {0x1760;}' unless defined(&ALE_TX_MIB_BASE);
    eval 'sub ALE_HOST_RXF0_PAGEOFF () {0x1800;}' unless defined(&ALE_HOST_RXF0_PAGEOFF);
    eval 'sub ALE_TPD_CONS_IDX () {0x1804;}' unless defined(&ALE_TPD_CONS_IDX);
    eval 'sub ALE_HOST_RXF1_PAGEOFF () {0x1808;}' unless defined(&ALE_HOST_RXF1_PAGEOFF);
    eval 'sub ALE_HOST_RXF2_PAGEOFF () {0x180c;}' unless defined(&ALE_HOST_RXF2_PAGEOFF);
    eval 'sub ALE_HOST_RXF3_PAGEOFF () {0x1810;}' unless defined(&ALE_HOST_RXF3_PAGEOFF);
    eval 'sub ALE_RXF0_CMB0_ADDR_LO () {0x1820;}' unless defined(&ALE_RXF0_CMB0_ADDR_LO);
    eval 'sub ALE_RXF0_CMB1_ADDR_LO () {0x1824;}' unless defined(&ALE_RXF0_CMB1_ADDR_LO);
    eval 'sub ALE_RXF1_CMB0_ADDR_LO () {0x1828;}' unless defined(&ALE_RXF1_CMB0_ADDR_LO);
    eval 'sub ALE_RXF1_CMB1_ADDR_LO () {0x182c;}' unless defined(&ALE_RXF1_CMB1_ADDR_LO);
    eval 'sub ALE_RXF2_CMB0_ADDR_LO () {0x1830;}' unless defined(&ALE_RXF2_CMB0_ADDR_LO);
    eval 'sub ALE_RXF2_CMB1_ADDR_LO () {0x1834;}' unless defined(&ALE_RXF2_CMB1_ADDR_LO);
    eval 'sub ALE_RXF3_CMB0_ADDR_LO () {0x1838;}' unless defined(&ALE_RXF3_CMB0_ADDR_LO);
    eval 'sub ALE_RXF3_CMB1_ADDR_LO () {0x183c;}' unless defined(&ALE_RXF3_CMB1_ADDR_LO);
    eval 'sub ALE_TX_CMB_ADDR_LO () {0x1840;}' unless defined(&ALE_TX_CMB_ADDR_LO);
    eval 'sub ALE_SMB_ADDR_LO () {0x1844;}' unless defined(&ALE_SMB_ADDR_LO);
    eval 'sub ALE_RD_SEQNO_MASK () {0xffff;}' unless defined(&ALE_RD_SEQNO_MASK);
    eval 'sub ALE_RD_HASH_MASK () {0xffff0000;}' unless defined(&ALE_RD_HASH_MASK);
    eval 'sub ALE_RD_SEQNO_SHIFT () {0;}' unless defined(&ALE_RD_SEQNO_SHIFT);
    eval 'sub ALE_RD_HASH_SHIFT () {16;}' unless defined(&ALE_RD_HASH_SHIFT);
    eval 'sub ALE_RX_SEQNO {
        my($x) = @_;
	    eval q(((($x) &  &ALE_RD_SEQNO_MASK) >>  &ALE_RD_SEQNO_SHIFT));
    }' unless defined(&ALE_RX_SEQNO);
    eval 'sub ALE_RD_CSUM_MASK () {0xffff;}' unless defined(&ALE_RD_CSUM_MASK);
    eval 'sub ALE_RD_LEN_MASK () {0x3fff0000;}' unless defined(&ALE_RD_LEN_MASK);
    eval 'sub ALE_RD_CPU_MASK () {0xc0000000;}' unless defined(&ALE_RD_CPU_MASK);
    eval 'sub ALE_RD_CSUM_SHIFT () {0;}' unless defined(&ALE_RD_CSUM_SHIFT);
    eval 'sub ALE_RD_LEN_SHIFT () {16;}' unless defined(&ALE_RD_LEN_SHIFT);
    eval 'sub ALE_RD_CPU_SHIFT () {30;}' unless defined(&ALE_RD_CPU_SHIFT);
    eval 'sub ALE_RX_CSUM {
        my($x) = @_;
	    eval q(((($x) &  &ALE_RD_CSUM_MASK) >>  &ALE_RD_CSUM_SHIFT));
    }' unless defined(&ALE_RX_CSUM);
    eval 'sub ALE_RX_BYTES {
        my($x) = @_;
	    eval q(((($x) &  &ALE_RD_LEN_MASK) >>  &ALE_RD_LEN_SHIFT));
    }' unless defined(&ALE_RX_BYTES);
    eval 'sub ALE_RX_CPU {
        my($x) = @_;
	    eval q(((($x) &  &ALE_RD_CPU_MASK) >>  &ALE_RD_CPU_SHIFT));
    }' unless defined(&ALE_RX_CPU);
    eval 'sub ALE_RD_RSS_IPV4 () {0x1;}' unless defined(&ALE_RD_RSS_IPV4);
    eval 'sub ALE_RD_RSS_IPV4_TCP () {0x2;}' unless defined(&ALE_RD_RSS_IPV4_TCP);
    eval 'sub ALE_RD_RSS_IPV6 () {0x4;}' unless defined(&ALE_RD_RSS_IPV6);
    eval 'sub ALE_RD_RSS_IPV6_TCP () {0x8;}' unless defined(&ALE_RD_RSS_IPV6_TCP);
    eval 'sub ALE_RD_IPV6 () {0x10;}' unless defined(&ALE_RD_IPV6);
    eval 'sub ALE_RD_IPV4_FRAG () {0x20;}' unless defined(&ALE_RD_IPV4_FRAG);
    eval 'sub ALE_RD_IPV4_DF () {0x40;}' unless defined(&ALE_RD_IPV4_DF);
    eval 'sub ALE_RD_802_3 () {0x80;}' unless defined(&ALE_RD_802_3);
    eval 'sub ALE_RD_VLAN () {0x100;}' unless defined(&ALE_RD_VLAN);
    eval 'sub ALE_RD_ERROR () {0x200;}' unless defined(&ALE_RD_ERROR);
    eval 'sub ALE_RD_IPV4 () {0x400;}' unless defined(&ALE_RD_IPV4);
    eval 'sub ALE_RD_UDP () {0x800;}' unless defined(&ALE_RD_UDP);
    eval 'sub ALE_RD_TCP () {0x1000;}' unless defined(&ALE_RD_TCP);
    eval 'sub ALE_RD_BCAST () {0x2000;}' unless defined(&ALE_RD_BCAST);
    eval 'sub ALE_RD_MCAST () {0x4000;}' unless defined(&ALE_RD_MCAST);
    eval 'sub ALE_RD_PAUSE () {0x8000;}' unless defined(&ALE_RD_PAUSE);
    eval 'sub ALE_RD_CRC () {0x10000;}' unless defined(&ALE_RD_CRC);
    eval 'sub ALE_RD_CODE () {0x20000;}' unless defined(&ALE_RD_CODE);
    eval 'sub ALE_RD_DRIBBLE () {0x40000;}' unless defined(&ALE_RD_DRIBBLE);
    eval 'sub ALE_RD_RUNT () {0x80000;}' unless defined(&ALE_RD_RUNT);
    eval 'sub ALE_RD_OFLOW () {0x100000;}' unless defined(&ALE_RD_OFLOW);
    eval 'sub ALE_RD_TRUNC () {0x200000;}' unless defined(&ALE_RD_TRUNC);
    eval 'sub ALE_RD_IPCSUM_NOK () {0x400000;}' unless defined(&ALE_RD_IPCSUM_NOK);
    eval 'sub ALE_RD_TCP_UDPCSUM_NOK () {0x800000;}' unless defined(&ALE_RD_TCP_UDPCSUM_NOK);
    eval 'sub ALE_RD_LENGTH_NOK () {0x1000000;}' unless defined(&ALE_RD_LENGTH_NOK);
    eval 'sub ALE_RD_DES_ADDR_FILTERED () {0x2000000;}' unless defined(&ALE_RD_DES_ADDR_FILTERED);
    eval 'sub ALE_RD_HASH_HI_MASK () {0xffff;}' unless defined(&ALE_RD_HASH_HI_MASK);
    eval 'sub ALE_RD_HASH_HI_SHIFT () {0;}' unless defined(&ALE_RD_HASH_HI_SHIFT);
    eval 'sub ALE_RD_VLAN_MASK () {0xffff0000;}' unless defined(&ALE_RD_VLAN_MASK);
    eval 'sub ALE_RD_VLAN_SHIFT () {16;}' unless defined(&ALE_RD_VLAN_SHIFT);
    eval 'sub ALE_RX_VLAN {
        my($x) = @_;
	    eval q(((($x) &  &ALE_RD_VLAN_MASK) >>  &ALE_RD_VLAN_SHIFT));
    }' unless defined(&ALE_RX_VLAN);
    eval 'sub ALE_RX_VLAN_TAG {
        my($x) = @_;
	    eval q(((($x) >> 4) | ((($x) & 7) << 13) | ((($x) & 8) << 9)));
    }' unless defined(&ALE_RX_VLAN_TAG);
    eval 'sub ALE_TD_VLAN_MASK () {0xffff0000;}' unless defined(&ALE_TD_VLAN_MASK);
    eval 'sub ALE_TD_PKT_INT () {0x8000;}' unless defined(&ALE_TD_PKT_INT);
    eval 'sub ALE_TD_DMA_INT () {0x4000;}' unless defined(&ALE_TD_DMA_INT);
    eval 'sub ALE_TD_BUFLEN_MASK () {0x3fff;}' unless defined(&ALE_TD_BUFLEN_MASK);
    eval 'sub ALE_TD_VLAN_SHIFT () {16;}' unless defined(&ALE_TD_VLAN_SHIFT);
    eval 'sub ALE_TX_VLAN_TAG {
        my($x) = @_;
	    eval q(((($x) << 4) | (($x) >> 13) | ((($x) >> 9) & 8)));
    }' unless defined(&ALE_TX_VLAN_TAG);
    eval 'sub ALE_TD_BUFLEN_SHIFT () {0;}' unless defined(&ALE_TD_BUFLEN_SHIFT);
    eval 'sub ALE_TX_BYTES {
        my($x) = @_;
	    eval q(((($x) <<  &ALE_TD_BUFLEN_SHIFT) &  &ALE_TD_BUFLEN_MASK));
    }' unless defined(&ALE_TX_BYTES);
    eval 'sub ALE_TD_MSS () {0xfff80000;}' unless defined(&ALE_TD_MSS);
    eval 'sub ALE_TD_TSO_HDR () {0x40000;}' unless defined(&ALE_TD_TSO_HDR);
    eval 'sub ALE_TD_TCPHDR_LEN () {0x3c000;}' unless defined(&ALE_TD_TCPHDR_LEN);
    eval 'sub ALE_TD_IPHDR_LEN () {0x3c00;}' unless defined(&ALE_TD_IPHDR_LEN);
    eval 'sub ALE_TD_IPV6HDR_LEN2 () {0x3c00;}' unless defined(&ALE_TD_IPV6HDR_LEN2);
    eval 'sub ALE_TD_LLC_SNAP () {0x200;}' unless defined(&ALE_TD_LLC_SNAP);
    eval 'sub ALE_TD_VLAN_TAGGED () {0x100;}' unless defined(&ALE_TD_VLAN_TAGGED);
    eval 'sub ALE_TD_UDPCSUM () {0x80;}' unless defined(&ALE_TD_UDPCSUM);
    eval 'sub ALE_TD_TCPCSUM () {0x40;}' unless defined(&ALE_TD_TCPCSUM);
    eval 'sub ALE_TD_IPCSUM () {0x20;}' unless defined(&ALE_TD_IPCSUM);
    eval 'sub ALE_TD_IPV6HDR_LEN1 () {0xe0;}' unless defined(&ALE_TD_IPV6HDR_LEN1);
    eval 'sub ALE_TD_TSO () {0x10;}' unless defined(&ALE_TD_TSO);
    eval 'sub ALE_TD_CXSUM () {0x8;}' unless defined(&ALE_TD_CXSUM);
    eval 'sub ALE_TD_INSERT_VLAN_TAG () {0x4;}' unless defined(&ALE_TD_INSERT_VLAN_TAG);
    eval 'sub ALE_TD_IPV6 () {0x2;}' unless defined(&ALE_TD_IPV6);
    eval 'sub ALE_TD_EOP () {0x1;}' unless defined(&ALE_TD_EOP);
    eval 'sub ALE_TD_CSUM_PLOADOFFSET () {0xff0000;}' unless defined(&ALE_TD_CSUM_PLOADOFFSET);
    eval 'sub ALE_TD_CSUM_XSUMOFFSET () {0xff000000;}' unless defined(&ALE_TD_CSUM_XSUMOFFSET);
    eval 'sub ALE_TD_CSUM_XSUMOFFSET_SHIFT () {24;}' unless defined(&ALE_TD_CSUM_XSUMOFFSET_SHIFT);
    eval 'sub ALE_TD_CSUM_PLOADOFFSET_SHIFT () {16;}' unless defined(&ALE_TD_CSUM_PLOADOFFSET_SHIFT);
    eval 'sub ALE_TD_MSS_SHIFT () {19;}' unless defined(&ALE_TD_MSS_SHIFT);
    eval 'sub ALE_TD_TCPHDR_LEN_SHIFT () {14;}' unless defined(&ALE_TD_TCPHDR_LEN_SHIFT);
    eval 'sub ALE_TD_IPHDR_LEN_SHIFT () {10;}' unless defined(&ALE_TD_IPHDR_LEN_SHIFT);
    eval 'sub ALE_TX_RING_CNT () {256;}' unless defined(&ALE_TX_RING_CNT);
    eval 'sub ALE_TX_RING_CNT_MIN () {32;}' unless defined(&ALE_TX_RING_CNT_MIN);
    eval 'sub ALE_TX_RING_CNT_MAX () {1020;}' unless defined(&ALE_TX_RING_CNT_MAX);
    eval 'sub ALE_TX_RING_ALIGN () {8;}' unless defined(&ALE_TX_RING_ALIGN);
    eval 'sub ALE_RX_PAGE_ALIGN () {32;}' unless defined(&ALE_RX_PAGE_ALIGN);
    eval 'sub ALE_RX_PAGES () {2;}' unless defined(&ALE_RX_PAGES);
    eval 'sub ALE_CMB_ALIGN () {32;}' unless defined(&ALE_CMB_ALIGN);
    eval 'sub ALE_TSO_MAXSEGSIZE () {4096;}' unless defined(&ALE_TSO_MAXSEGSIZE);
    eval 'sub ALE_TSO_MAXSIZE () {(65535+ $sizeof{\'struct ether_vlan_header\'});}' unless defined(&ALE_TSO_MAXSIZE);
    eval 'sub ALE_MAXTXSEGS () {32;}' unless defined(&ALE_MAXTXSEGS);
    eval 'sub ALE_ADDR_LO {
        my($x) = @_;
	    eval q((( &uint64_t) ($x) & 0xffffffff));
    }' unless defined(&ALE_ADDR_LO);
    eval 'sub ALE_ADDR_HI {
        my($x) = @_;
	    eval q((( &uint64_t) ($x) >> 32));
    }' unless defined(&ALE_ADDR_HI);
    eval 'sub ALE_TX_DESC_HIWAT () {( &ALE_TX_RING_CNT - (( &ALE_TX_RING_CNT * 4) / 10));}' unless defined(&ALE_TX_DESC_HIWAT);
    eval 'sub ALE_MSI_MESSAGES () {1;}' unless defined(&ALE_MSI_MESSAGES);
    eval 'sub ALE_MSIX_MESSAGES () {1;}' unless defined(&ALE_MSIX_MESSAGES);
    eval 'sub ALE_JUMBO_FRAMELEN () {8132;}' unless defined(&ALE_JUMBO_FRAMELEN);
    eval 'sub ALE_JUMBO_MTU () {( &ALE_JUMBO_FRAMELEN - $sizeof{\'struct ether_vlan_header\'} -  &ETHER_CRC_LEN);}' unless defined(&ALE_JUMBO_MTU);
    eval 'sub ALE_MAX_FRAMELEN () {( &ETHER_MAX_LEN +  &EVL_ENCAPLEN);}' unless defined(&ALE_MAX_FRAMELEN);
    eval 'sub ALE_DESC_INC {
        my($x, $y) = @_;
	    eval q((($x) = (($x) + 1) % ($y)));
    }' unless defined(&ALE_DESC_INC);
    eval 'sub ALE_TX_RING_SZ () {($sizeof{\'struct tx_desc\'} *  &ALE_TX_RING_CNT);}' unless defined(&ALE_TX_RING_SZ);
    eval 'sub ALE_RX_PAGE_SZ_MIN () {(8* 1024);}' unless defined(&ALE_RX_PAGE_SZ_MIN);
    eval 'sub ALE_RX_PAGE_SZ_MAX () {(1024* 1024);}' unless defined(&ALE_RX_PAGE_SZ_MAX);
    eval 'sub ALE_RX_FRAMES_PAGE () {128;}' unless defined(&ALE_RX_FRAMES_PAGE);
    eval 'sub ALE_RX_PAGE_SZ () {( &roundup( &ALE_MAX_FRAMELEN,  &ALE_RX_PAGE_ALIGN) *  &ALE_RX_FRAMES_PAGE);}' unless defined(&ALE_RX_PAGE_SZ);
    eval 'sub ALE_TX_CMB_SZ () {($sizeof{ &uint32_t});}' unless defined(&ALE_TX_CMB_SZ);
    eval 'sub ALE_RX_CMB_SZ () {($sizeof{ &uint32_t});}' unless defined(&ALE_RX_CMB_SZ);
    eval 'sub ALE_PROC_MIN () {( &ALE_RX_FRAMES_PAGE / 4);}' unless defined(&ALE_PROC_MIN);
    eval 'sub ALE_PROC_MAX () {(( &ALE_RX_PAGE_SZ *  &ALE_RX_PAGES) /  &ETHER_MAX_LEN);}' unless defined(&ALE_PROC_MAX);
    eval 'sub ALE_PROC_DEFAULT () {( &ALE_PROC_MAX / 4);}' unless defined(&ALE_PROC_DEFAULT);
    eval 'sub ALE_FLAG_PCIE () {0x1;}' unless defined(&ALE_FLAG_PCIE);
    eval 'sub ALE_FLAG_PCIX () {0x2;}' unless defined(&ALE_FLAG_PCIX);
    eval 'sub ALE_FLAG_MSI () {0x4;}' unless defined(&ALE_FLAG_MSI);
    eval 'sub ALE_FLAG_MSIX () {0x8;}' unless defined(&ALE_FLAG_MSIX);
    eval 'sub ALE_FLAG_PMCAP () {0x10;}' unless defined(&ALE_FLAG_PMCAP);
    eval 'sub ALE_FLAG_FASTETHER () {0x20;}' unless defined(&ALE_FLAG_FASTETHER);
    eval 'sub ALE_FLAG_JUMBO () {0x40;}' unless defined(&ALE_FLAG_JUMBO);
    eval 'sub ALE_FLAG_RXCSUM_BUG () {0x80;}' unless defined(&ALE_FLAG_RXCSUM_BUG);
    eval 'sub ALE_FLAG_TXCSUM_BUG () {0x100;}' unless defined(&ALE_FLAG_TXCSUM_BUG);
    eval 'sub ALE_FLAG_TXCMB_BUG () {0x200;}' unless defined(&ALE_FLAG_TXCMB_BUG);
    eval 'sub ALE_FLAG_DETACH () {0x4000;}' unless defined(&ALE_FLAG_DETACH);
    eval 'sub ALE_FLAG_LINK () {0x8000;}' unless defined(&ALE_FLAG_LINK);
    eval 'sub CSR_WRITE_4 {
        my($_sc, $reg, $val) = @_;
	    eval q( &bus_space_write_4(( &sc)-> &sc_mem_bt, ( &sc)-> &sc_mem_bh, ($reg), ($val)));
    }' unless defined(&CSR_WRITE_4);
    eval 'sub CSR_WRITE_2 {
        my($_sc, $reg, $val) = @_;
	    eval q( &bus_space_write_2(( &sc)-> &sc_mem_bt, ( &sc)-> &sc_mem_bh, ($reg), ($val)));
    }' unless defined(&CSR_WRITE_2);
    eval 'sub CSR_WRITE_1 {
        my($_sc, $reg, $val) = @_;
	    eval q( &bus_space_write_1(( &sc)-> &sc_mem_bt, ( &sc)-> &sc_mem_bh, ($reg), ($val)));
    }' unless defined(&CSR_WRITE_1);
    eval 'sub CSR_READ_2 {
        my($_sc, $reg) = @_;
	    eval q( &bus_space_read_2(( &sc)-> &sc_mem_bt, ( &sc)-> &sc_mem_bh, ($reg)));
    }' unless defined(&CSR_READ_2);
    eval 'sub CSR_READ_4 {
        my($_sc, $reg) = @_;
	    eval q( &bus_space_read_4(( &sc)-> &sc_mem_bt, ( &sc)-> &sc_mem_bh, ($reg)));
    }' unless defined(&CSR_READ_4);
    eval 'sub ALE_TX_TIMEOUT () {5;}' unless defined(&ALE_TX_TIMEOUT);
    eval 'sub ALE_RESET_TIMEOUT () {100;}' unless defined(&ALE_RESET_TIMEOUT);
    eval 'sub ALE_TIMEOUT () {1000;}' unless defined(&ALE_TIMEOUT);
    eval 'sub ALE_PHY_TIMEOUT () {1000;}' unless defined(&ALE_PHY_TIMEOUT);
}
1;
