require '_h2ph_pre.ph';

no warnings qw(redefine misc);

unless(defined(&_I915_DRM_H_)) {
    eval 'sub _I915_DRM_H_ () {1;}' unless defined(&_I915_DRM_H_);
    require './dev/pci/drm/drm.ph';
    eval 'sub I915_NR_TEX_REGIONS () {255;}' unless defined(&I915_NR_TEX_REGIONS);
    eval 'sub I915_LOG_MIN_TEX_REGION_SIZE () {14;}' unless defined(&I915_LOG_MIN_TEX_REGION_SIZE);
    eval("sub I915_INIT_DMA () { 0x01; }") unless defined(&I915_INIT_DMA);
    eval("sub I915_CLEANUP_DMA () { 0x02; }") unless defined(&I915_CLEANUP_DMA);
    eval("sub I915_RESUME_DMA () { 0x03; }") unless defined(&I915_RESUME_DMA);
    eval 'sub I915_BOX_RING_EMPTY () {0x1;}' unless defined(&I915_BOX_RING_EMPTY);
    eval 'sub I915_BOX_FLIP () {0x2;}' unless defined(&I915_BOX_FLIP);
    eval 'sub I915_BOX_WAIT () {0x4;}' unless defined(&I915_BOX_WAIT);
    eval 'sub I915_BOX_TEXTURE_LOAD () {0x8;}' unless defined(&I915_BOX_TEXTURE_LOAD);
    eval 'sub I915_BOX_LOST_CONTEXT () {0x10;}' unless defined(&I915_BOX_LOST_CONTEXT);
    eval 'sub DRM_I915_INIT () {0x;}' unless defined(&DRM_I915_INIT);
    eval 'sub DRM_I915_FLUSH () {0x1;}' unless defined(&DRM_I915_FLUSH);
    eval 'sub DRM_I915_FLIP () {0x2;}' unless defined(&DRM_I915_FLIP);
    eval 'sub DRM_I915_BATCHBUFFER () {0x3;}' unless defined(&DRM_I915_BATCHBUFFER);
    eval 'sub DRM_I915_IRQ_EMIT () {0x4;}' unless defined(&DRM_I915_IRQ_EMIT);
    eval 'sub DRM_I915_IRQ_WAIT () {0x5;}' unless defined(&DRM_I915_IRQ_WAIT);
    eval 'sub DRM_I915_GETPARAM () {0x6;}' unless defined(&DRM_I915_GETPARAM);
    eval 'sub DRM_I915_SETPARAM () {0x7;}' unless defined(&DRM_I915_SETPARAM);
    eval 'sub DRM_I915_ALLOC () {0x8;}' unless defined(&DRM_I915_ALLOC);
    eval 'sub DRM_I915_FREE () {0x9;}' unless defined(&DRM_I915_FREE);
    eval 'sub DRM_I915_INIT_HEAP () {0xa;}' unless defined(&DRM_I915_INIT_HEAP);
    eval 'sub DRM_I915_CMDBUFFER () {0xb;}' unless defined(&DRM_I915_CMDBUFFER);
    eval 'sub DRM_I915_DESTROY_HEAP () {0xc;}' unless defined(&DRM_I915_DESTROY_HEAP);
    eval 'sub DRM_I915_SET_VBLANK_PIPE () {0xd;}' unless defined(&DRM_I915_SET_VBLANK_PIPE);
    eval 'sub DRM_I915_GET_VBLANK_PIPE () {0xe;}' unless defined(&DRM_I915_GET_VBLANK_PIPE);
    eval 'sub DRM_I915_VBLANK_SWAP () {0xf;}' unless defined(&DRM_I915_VBLANK_SWAP);
    eval 'sub DRM_I915_HWS_ADDR () {0x11;}' unless defined(&DRM_I915_HWS_ADDR);
    eval 'sub DRM_I915_GEM_INIT () {0x13;}' unless defined(&DRM_I915_GEM_INIT);
    eval 'sub DRM_I915_GEM_EXECBUFFER () {0x14;}' unless defined(&DRM_I915_GEM_EXECBUFFER);
    eval 'sub DRM_I915_GEM_PIN () {0x15;}' unless defined(&DRM_I915_GEM_PIN);
    eval 'sub DRM_I915_GEM_UNPIN () {0x16;}' unless defined(&DRM_I915_GEM_UNPIN);
    eval 'sub DRM_I915_GEM_BUSY () {0x17;}' unless defined(&DRM_I915_GEM_BUSY);
    eval 'sub DRM_I915_GEM_THROTTLE () {0x18;}' unless defined(&DRM_I915_GEM_THROTTLE);
    eval 'sub DRM_I915_GEM_ENTERVT () {0x19;}' unless defined(&DRM_I915_GEM_ENTERVT);
    eval 'sub DRM_I915_GEM_LEAVEVT () {0x1a;}' unless defined(&DRM_I915_GEM_LEAVEVT);
    eval 'sub DRM_I915_GEM_CREATE () {0x1b;}' unless defined(&DRM_I915_GEM_CREATE);
    eval 'sub DRM_I915_GEM_PREAD () {0x1c;}' unless defined(&DRM_I915_GEM_PREAD);
    eval 'sub DRM_I915_GEM_PWRITE () {0x1d;}' unless defined(&DRM_I915_GEM_PWRITE);
    eval 'sub DRM_I915_GEM_MMAP () {0x1e;}' unless defined(&DRM_I915_GEM_MMAP);
    eval 'sub DRM_I915_GEM_SET_DOMAIN () {0x1f;}' unless defined(&DRM_I915_GEM_SET_DOMAIN);
    eval 'sub DRM_I915_GEM_SW_FINISH () {0x20;}' unless defined(&DRM_I915_GEM_SW_FINISH);
    eval 'sub DRM_I915_GEM_SET_TILING () {0x21;}' unless defined(&DRM_I915_GEM_SET_TILING);
    eval 'sub DRM_I915_GEM_GET_TILING () {0x22;}' unless defined(&DRM_I915_GEM_GET_TILING);
    eval 'sub DRM_I915_GEM_GET_APERTURE () {0x23;}' unless defined(&DRM_I915_GEM_GET_APERTURE);
    eval 'sub DRM_IOCTL_I915_INIT () { &DRM_IOW(  &DRM_COMMAND_BASE +  &DRM_I915_INIT,  &drm_i915_init_t);}' unless defined(&DRM_IOCTL_I915_INIT);
    eval 'sub DRM_IOCTL_I915_FLUSH () { &DRM_IO (  &DRM_COMMAND_BASE +  &DRM_I915_FLUSH);}' unless defined(&DRM_IOCTL_I915_FLUSH);
    eval 'sub DRM_IOCTL_I915_FLIP () { &DRM_IO (  &DRM_COMMAND_BASE +  &DRM_I915_FLIP);}' unless defined(&DRM_IOCTL_I915_FLIP);
    eval 'sub DRM_IOCTL_I915_BATCHBUFFER () { &DRM_IOW(  &DRM_COMMAND_BASE +  &DRM_I915_BATCHBUFFER,  &drm_i915_batchbuffer_t);}' unless defined(&DRM_IOCTL_I915_BATCHBUFFER);
    eval 'sub DRM_IOCTL_I915_IRQ_EMIT () { &DRM_IOWR( &DRM_COMMAND_BASE +  &DRM_I915_IRQ_EMIT,  &drm_i915_irq_emit_t);}' unless defined(&DRM_IOCTL_I915_IRQ_EMIT);
    eval 'sub DRM_IOCTL_I915_IRQ_WAIT () { &DRM_IOW(  &DRM_COMMAND_BASE +  &DRM_I915_IRQ_WAIT,  &drm_i915_irq_wait_t);}' unless defined(&DRM_IOCTL_I915_IRQ_WAIT);
    eval 'sub DRM_IOCTL_I915_GETPARAM () { &DRM_IOWR( &DRM_COMMAND_BASE +  &DRM_I915_GETPARAM,  &drm_i915_getparam_t);}' unless defined(&DRM_IOCTL_I915_GETPARAM);
    eval 'sub DRM_IOCTL_I915_SETPARAM () { &DRM_IOW(  &DRM_COMMAND_BASE +  &DRM_I915_SETPARAM,  &drm_i915_setparam_t);}' unless defined(&DRM_IOCTL_I915_SETPARAM);
    eval 'sub DRM_IOCTL_I915_ALLOC () { &DRM_IOWR( &DRM_COMMAND_BASE +  &DRM_I915_ALLOC,  &drm_i915_mem_alloc_t);}' unless defined(&DRM_IOCTL_I915_ALLOC);
    eval 'sub DRM_IOCTL_I915_FREE () { &DRM_IOW(  &DRM_COMMAND_BASE +  &DRM_I915_FREE,  &drm_i915_mem_free_t);}' unless defined(&DRM_IOCTL_I915_FREE);
    eval 'sub DRM_IOCTL_I915_INIT_HEAP () { &DRM_IOW(  &DRM_COMMAND_BASE +  &DRM_I915_INIT_HEAP,  &drm_i915_mem_init_heap_t);}' unless defined(&DRM_IOCTL_I915_INIT_HEAP);
    eval 'sub DRM_IOCTL_I915_CMDBUFFER () { &DRM_IOW(  &DRM_COMMAND_BASE +  &DRM_I915_CMDBUFFER,  &drm_i915_cmdbuffer_t);}' unless defined(&DRM_IOCTL_I915_CMDBUFFER);
    eval 'sub DRM_IOCTL_I915_DESTROY_HEAP () { &DRM_IOW(  &DRM_COMMAND_BASE +  &DRM_I915_DESTROY_HEAP,  &drm_i915_mem_destroy_heap_t);}' unless defined(&DRM_IOCTL_I915_DESTROY_HEAP);
    eval 'sub DRM_IOCTL_I915_SET_VBLANK_PIPE () { &DRM_IOW(  &DRM_COMMAND_BASE +  &DRM_I915_SET_VBLANK_PIPE,  &drm_i915_vblank_pipe_t);}' unless defined(&DRM_IOCTL_I915_SET_VBLANK_PIPE);
    eval 'sub DRM_IOCTL_I915_GET_VBLANK_PIPE () { &DRM_IOR(  &DRM_COMMAND_BASE +  &DRM_I915_GET_VBLANK_PIPE,  &drm_i915_vblank_pipe_t);}' unless defined(&DRM_IOCTL_I915_GET_VBLANK_PIPE);
    eval 'sub DRM_IOCTL_I915_VBLANK_SWAP () { &DRM_IOWR( &DRM_COMMAND_BASE +  &DRM_I915_VBLANK_SWAP,  &drm_i915_vblank_swap_t);}' unless defined(&DRM_IOCTL_I915_VBLANK_SWAP);
    eval 'sub DRM_IOCTL_I915_HWS_ADDR () { &DRM_IOW( &DRM_COMMAND_BASE +  &DRM_I915_HWS_ADDR,  &drm_i915_hws_addr_t);}' unless defined(&DRM_IOCTL_I915_HWS_ADDR);
    eval 'sub DRM_IOCTL_I915_GEM_INIT () { &DRM_IOW( &DRM_COMMAND_BASE +  &DRM_I915_GEM_INIT, \'struct drm_i915_gem_init\');}' unless defined(&DRM_IOCTL_I915_GEM_INIT);
    eval 'sub DRM_IOCTL_I915_GEM_EXECBUFFER () { &DRM_IOW( &DRM_COMMAND_BASE +  &DRM_I915_GEM_EXECBUFFER, \'struct drm_i915_gem_execbuffer\');}' unless defined(&DRM_IOCTL_I915_GEM_EXECBUFFER);
    eval 'sub DRM_IOCTL_I915_GEM_PIN () { &DRM_IOWR( &DRM_COMMAND_BASE +  &DRM_I915_GEM_PIN, \'struct drm_i915_gem_pin\');}' unless defined(&DRM_IOCTL_I915_GEM_PIN);
    eval 'sub DRM_IOCTL_I915_GEM_UNPIN () { &DRM_IOW( &DRM_COMMAND_BASE +  &DRM_I915_GEM_UNPIN, \'struct drm_i915_gem_unpin\');}' unless defined(&DRM_IOCTL_I915_GEM_UNPIN);
    eval 'sub DRM_IOCTL_I915_GEM_BUSY () { &DRM_IOWR( &DRM_COMMAND_BASE +  &DRM_I915_GEM_BUSY, \'struct drm_i915_gem_busy\');}' unless defined(&DRM_IOCTL_I915_GEM_BUSY);
    eval 'sub DRM_IOCTL_I915_GEM_THROTTLE () { &DRM_IO (  &DRM_COMMAND_BASE +  &DRM_I915_GEM_THROTTLE);}' unless defined(&DRM_IOCTL_I915_GEM_THROTTLE);
    eval 'sub DRM_IOCTL_I915_GEM_ENTERVT () { &DRM_IO( &DRM_COMMAND_BASE +  &DRM_I915_GEM_ENTERVT);}' unless defined(&DRM_IOCTL_I915_GEM_ENTERVT);
    eval 'sub DRM_IOCTL_I915_GEM_LEAVEVT () { &DRM_IO( &DRM_COMMAND_BASE +  &DRM_I915_GEM_LEAVEVT);}' unless defined(&DRM_IOCTL_I915_GEM_LEAVEVT);
    eval 'sub DRM_IOCTL_I915_GEM_CREATE () { &DRM_IOWR( &DRM_COMMAND_BASE +  &DRM_I915_GEM_CREATE, \'struct drm_i915_gem_create\');}' unless defined(&DRM_IOCTL_I915_GEM_CREATE);
    eval 'sub DRM_IOCTL_I915_GEM_PREAD () { &DRM_IOW ( &DRM_COMMAND_BASE +  &DRM_I915_GEM_PREAD, \'struct drm_i915_gem_pread\');}' unless defined(&DRM_IOCTL_I915_GEM_PREAD);
    eval 'sub DRM_IOCTL_I915_GEM_PWRITE () { &DRM_IOW ( &DRM_COMMAND_BASE +  &DRM_I915_GEM_PWRITE, \'struct drm_i915_gem_pwrite\');}' unless defined(&DRM_IOCTL_I915_GEM_PWRITE);
    eval 'sub DRM_IOCTL_I915_GEM_MMAP () { &DRM_IOWR( &DRM_COMMAND_BASE +  &DRM_I915_GEM_MMAP, \'struct drm_i915_gem_mmap\');}' unless defined(&DRM_IOCTL_I915_GEM_MMAP);
    eval 'sub DRM_IOCTL_I915_GEM_SET_DOMAIN () { &DRM_IOW ( &DRM_COMMAND_BASE +  &DRM_I915_GEM_SET_DOMAIN, \'struct drm_i915_gem_set_domain\');}' unless defined(&DRM_IOCTL_I915_GEM_SET_DOMAIN);
    eval 'sub DRM_IOCTL_I915_GEM_SW_FINISH () { &DRM_IOW ( &DRM_COMMAND_BASE +  &DRM_I915_GEM_SW_FINISH, \'struct drm_i915_gem_sw_finish\');}' unless defined(&DRM_IOCTL_I915_GEM_SW_FINISH);
    eval 'sub DRM_IOCTL_I915_GEM_SET_TILING () { &DRM_IOWR ( &DRM_COMMAND_BASE +  &DRM_I915_GEM_SET_TILING, \'struct drm_i915_gem_set_tiling\');}' unless defined(&DRM_IOCTL_I915_GEM_SET_TILING);
    eval 'sub DRM_IOCTL_I915_GEM_GET_TILING () { &DRM_IOWR ( &DRM_COMMAND_BASE +  &DRM_I915_GEM_GET_TILING, \'struct drm_i915_gem_get_tiling\');}' unless defined(&DRM_IOCTL_I915_GEM_GET_TILING);
    eval 'sub DRM_IOCTL_I915_GEM_GET_APERTURE () { &DRM_IOR ( &DRM_COMMAND_BASE +  &DRM_I915_GEM_GET_APERTURE, \'struct drm_i915_gem_get_aperture\');}' unless defined(&DRM_IOCTL_I915_GEM_GET_APERTURE);
    eval 'sub I915_PARAM_IRQ_ACTIVE () {1;}' unless defined(&I915_PARAM_IRQ_ACTIVE);
    eval 'sub I915_PARAM_ALLOW_BATCHBUFFER () {2;}' unless defined(&I915_PARAM_ALLOW_BATCHBUFFER);
    eval 'sub I915_PARAM_LAST_DISPATCH () {3;}' unless defined(&I915_PARAM_LAST_DISPATCH);
    eval 'sub I915_PARAM_CHIPSET_ID () {4;}' unless defined(&I915_PARAM_CHIPSET_ID);
    eval 'sub I915_PARAM_HAS_GEM () {5;}' unless defined(&I915_PARAM_HAS_GEM);
    eval 'sub I915_PARAM_NUM_FENCES_AVAIL () {6;}' unless defined(&I915_PARAM_NUM_FENCES_AVAIL);
    eval 'sub I915_SETPARAM_USE_MI_BATCHBUFFER_START () {1;}' unless defined(&I915_SETPARAM_USE_MI_BATCHBUFFER_START);
    eval 'sub I915_SETPARAM_TEX_LRU_LOG_GRANULARITY () {2;}' unless defined(&I915_SETPARAM_TEX_LRU_LOG_GRANULARITY);
    eval 'sub I915_SETPARAM_ALLOW_BATCHBUFFER () {3;}' unless defined(&I915_SETPARAM_ALLOW_BATCHBUFFER);
    eval 'sub I915_SETPARAM_NUM_USED_FENCES () {4;}' unless defined(&I915_SETPARAM_NUM_USED_FENCES);
    eval 'sub I915_MEM_REGION_AGP () {1;}' unless defined(&I915_MEM_REGION_AGP);
    eval 'sub DRM_I915_VBLANK_PIPE_A () {1;}' unless defined(&DRM_I915_VBLANK_PIPE_A);
    eval 'sub DRM_I915_VBLANK_PIPE_B () {2;}' unless defined(&DRM_I915_VBLANK_PIPE_B);
    eval 'sub I915_GEM_DOMAIN_CPU () {0x1;}' unless defined(&I915_GEM_DOMAIN_CPU);
    eval 'sub I915_GEM_DOMAIN_RENDER () {0x2;}' unless defined(&I915_GEM_DOMAIN_RENDER);
    eval 'sub I915_GEM_DOMAIN_SAMPLER () {0x4;}' unless defined(&I915_GEM_DOMAIN_SAMPLER);
    eval 'sub I915_GEM_DOMAIN_COMMAND () {0x8;}' unless defined(&I915_GEM_DOMAIN_COMMAND);
    eval 'sub I915_GEM_DOMAIN_INSTRUCTION () {0x10;}' unless defined(&I915_GEM_DOMAIN_INSTRUCTION);
    eval 'sub I915_GEM_DOMAIN_VERTEX () {0x20;}' unless defined(&I915_GEM_DOMAIN_VERTEX);
    eval 'sub I915_GEM_DOMAIN_GTT () {0x40;}' unless defined(&I915_GEM_DOMAIN_GTT);
    eval 'sub I915_TILING_NONE () {0;}' unless defined(&I915_TILING_NONE);
    eval 'sub I915_TILING_X () {1;}' unless defined(&I915_TILING_X);
    eval 'sub I915_TILING_Y () {2;}' unless defined(&I915_TILING_Y);
    eval 'sub I915_BIT_6_SWIZZLE_NONE () {0;}' unless defined(&I915_BIT_6_SWIZZLE_NONE);
    eval 'sub I915_BIT_6_SWIZZLE_9 () {1;}' unless defined(&I915_BIT_6_SWIZZLE_9);
    eval 'sub I915_BIT_6_SWIZZLE_9_10 () {2;}' unless defined(&I915_BIT_6_SWIZZLE_9_10);
    eval 'sub I915_BIT_6_SWIZZLE_9_11 () {3;}' unless defined(&I915_BIT_6_SWIZZLE_9_11);
    eval 'sub I915_BIT_6_SWIZZLE_9_10_11 () {4;}' unless defined(&I915_BIT_6_SWIZZLE_9_10_11);
    eval 'sub I915_BIT_6_SWIZZLE_UNKNOWN () {5;}' unless defined(&I915_BIT_6_SWIZZLE_UNKNOWN);
}
1;
